Inventor · disambiguated record
Kevin E. Sallese
Also filed as: SALLESE KEVIN E · SALLESE KEVIN ERNEST
19 granted patents·47 citations·filing 1997–2022
91Inventor score
Top patents by PatentIndex Score
19 records- 0189US10489086B1Reducing read errors by performing mitigation reads to blocks of non-volatile memoryIBM·Filed 2018·Granted Nov 26, 2019·7 cites·19 claims
- 0288US9298549B2Read buffer architecture supporting integrated XOR-reconstructed and read-retry for non-volatile random access memory (NVRAM) systemsIBM·Filed 2013·Granted Mar 29, 2016·12 cites·20 claims
- 0386US9400745B2Physical address management in solid state memoryIBM·Filed 2013·Granted Jul 26, 2016·6 cites·18 claims
- 0481US7430706B1Diagonal interleaved parity calculatorLATTICE SEMICONDUCTOR CORP·Filed 2007·Granted Sep 30, 2008·12 cites·14 claims
- 0577US10770155B2Determining a read apparent voltage infector page and infected pageIBM·Filed 2018·Granted Sep 8, 2020·2 cites·20 claims
- 0671US11036427B2Using content addressable memory to perform read-modify-write operations in non-volatile random access memory (NVRAM)IBM·Filed 2019·Granted Jun 15, 2021·1 cites·18 claims
- 0770US10552243B2Corrupt logical block addressing recovery schemeIBM·Filed 2017·Granted Feb 4, 2020·1 cites·19 claims
- 0862US10289304B2Physical address management in solid state memory by tracking pending reads therefromIBM·Filed 2018·Granted May 14, 2019·0 cites·20 claims
- 0961US9996266B2Physical address management in solid state memoryIBM·Filed 2017·Granted Jun 12, 2018·0 cites·20 claims
- 1060US11880299B2Calendar based flash command scheduler for dynamic quality of service scheduling and bandwidth allocationsIBM·Filed 2022·Granted Jan 23, 2024·0 cites·20 claims
- 1158US9857977B2Physical address management in solid state memoryIBM·Filed 2016·Granted Jan 2, 2018·0 cites·20 claims
- 1257US11880300B2Generating multi-plane reads to read pages on planes of a storage die for a page to readIBM·Filed 2022·Granted Jan 23, 2024·0 cites·20 claims
- 1352US11086565B2Reducing effects of read array operations of read apparent voltageIBM·Filed 2018·Granted Aug 10, 2021·0 cites·20 claims
- 1451US10169145B2Read buffer architecture supporting integrated XOR-reconstructed and read-retry for non-volatile random access memory (NVRAM) systemsIBM·Filed 2016·Granted Jan 1, 2019·0 cites·20 claims
- 1550US11301170B2Performing sub-logical page write operations in non-volatile random access memory (NVRAM) using pre-populated read-modify-write (RMW) buffersIBM·Filed 2020·Granted Apr 12, 2022·0 cites·20 claims
- 1650US11048571B2Selectively performing multi-plane read operations in non-volatile memoryIBM·Filed 2018·Granted Jun 29, 2021·0 cites·15 claims
- 1747US7191388B1Fast diagonal interleaved parity (DIP) calculatorLATTICE SEMICONDUCTOR CORP·Filed 2004·Granted Mar 13, 2007·4 cites·16 claims
- 1843US6940309B1Programmable logic device with a memory-based finite state machineLATTICE SEMICONDUCTOR CORP·Filed 2003·Granted Sep 6, 2005·0 cites·20 claims
- 1922US6075785AApparatus and method for providing memory address interchanging for high speed memory accessesLUCENT TECHNOLOGIES INC·Filed 1997·Granted Jun 13, 2000·2 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →