Inventor · disambiguated record
W. Eric Boyd
Also filed as: BOYD W ERIC
20 granted patents·8 pending applications·257 citations·filing 2005–2016
93Inventor score
Top patents by PatentIndex Score
28 records- 0196US7335576B2Method for precision integrated circuit die singulation using differential etch ratesIRVINE SENSORS CORP·Filed 2005·Granted Feb 26, 2008·61 cites·14 claims
- 0292US7235785B2Imaging device with multiple fields of view incorporating memory-based temperature compensation of an uncooled focal plane arrayIRVINE SENSORS CORP·Filed 2005·Granted Jun 26, 2007·144 cites·11 claims
- 0383US8415819B2Energy harvesting buoySAPIR ITZHAK·Filed 2010·Granted Apr 9, 2013·4 cites·11 claims
- 0481US7649386B2Field programmable gate array utilizing dedicated memory stacks in a vertical layer formatOZGUZ VOLKAN H·Filed 2007·Granted Jan 19, 2010·10 cites·40 claims
- 0580US7786562B2Stackable semiconductor chip layer comprising prefabricated trench interconnect viasOZGUZ VOLKAN·Filed 2005·Granted Aug 31, 2010·11 cites·34 claims
- 0678US8271262B1Portable lip reading sensor systemHSU YING·Filed 2009·Granted Sep 18, 2012·13 cites·6 claims
- 0770US7902879B2Field programmable gate array utilizing dedicated memory stacks in a vertical layer formatAPROLASE DEV CO LLC·Filed 2009·Granted Mar 8, 2011·4 cites·32 claims
- 0863US8637985B2Anti-tamper wrapper interconnect method and a deviceBINDRUP RANDY·Filed 2012·Granted Jan 28, 2014·2 cites·5 claims
- 0963USRE43877EMethod for precision integrated circuit die singulation using differential etch ratesLUDWIG DAVID·Filed 2010·Granted Dec 25, 2012·1 cites·42 claims
- 1062US7982300B2Stackable layer containing ball grid array packageAPROLASE DEV CO LLC·Filed 2010·Granted Jul 19, 2011·1 cites·20 claims
- 1159US9431275B2Wire bond through-via structure and methodBINDRUP RANDY·Filed 2011·Granted Aug 30, 2016·1 cites·12 claims
- 1257US7714426B1Ball grid array package format layers and structureGANN KEITH·Filed 2007·Granted May 11, 2010·1 cites·29 claims
- 1355US8586407B2Method for depackaging prepackaged integrated circuit die and a product from the methodLIEU PETER·Filed 2011·Granted Nov 19, 2013·2 cites·19 claims
- 1451US9728507B2Cap chip and reroute layer for stacked microelectronic moduleHE SAMBO·Filed 2012·Granted Aug 8, 2017·1 cites·11 claims
- 1549US8835218B2Stackable layer containing ball grid array packageGANN KEITH·Filed 2011·Granted Sep 16, 2014·0 cites·25 claims
- 1648US9741680B1Wire bond through-via structure and methodPFG IP LLC·Filed 2016·Granted Aug 22, 2017·0 cites·1 claims
- 1744US8637140B2Method for defining an electrically conductive metal structure on a three-dimensional element and a device made from the methodYAMAGUCHI JAMES·Filed 2011·Granted Jan 28, 2014·0 cites·5 claims
- 1842US9046322B2Self-calibrating targeting sightJUSTICE JAMES·Filed 2011·Granted Jun 2, 2015·1 cites·6 claims
- 1941US2010291735A1Stackable semiconductor chip layer comprising prefabricated trench interconnect viasOZGUZ VOLKAN·Filed 2010·Application pending·0 cites
- 2041US2011147568A1High density array module and connectorIRVINE SENSORS CORP·Filed 2010·Application pending·0 cites
- 2140US7777321B2Stacked microelectronic layer and module with three-axis channel T-connectsGANN KEITH D·Filed 2005·Granted Aug 17, 2010·0 cites·23 claims
- 2239US2013141137A1Stacked Physically Uncloneable Function Sense and Respond ModuleKRUTZIK CHRISTIAN·Filed 2012·Application pending·0 cites
- 2338US2011227603A1Secure Anti-Tamper Integrated Layer Security Device Comprising Nano-StructuresIRVINE SENSORS CORP·Filed 2011·Application pending·0 cites
- 2437US2011031982A1Tamper-resistant electronic circuit and module incorporating electrically conductive nano-structuresIRVINE SENSORS CORP·Filed 2010·Application pending·0 cites
- 2535US2012069528A1Method for Control of Solder Collapse in Stacked Microelectronic StructureBINDRUP RANDY·Filed 2011·Application pending·0 cites
- 2634US2012185636A1Tamper-Resistant Memory Device With Variable Data Transmission RateLEON JOHN·Filed 2012·Application pending·0 cites
- 2732US8609473B2Method for fabricating a neo-layer using stud bumped bare dieLIEU PETER·Filed 2011·Granted Dec 17, 2013·0 cites·1 claims
- 2831US2012211886A1Method for Fabricating a Small Footprint Chip-Scale Package and a Device Made from the MethodLIEU PETER·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →