Inventor · disambiguated record
Wan-Yih Lien
Also filed as: LIEN WAN-YIH
15 granted patents·1 pending application·442 citations·filing 1998–2004
94Inventor score
Files withVANGUARD INT SEMICONDUCT CORP7WORLDWIDE SEMICONDUCTOR MFG4TAIWAN SEMICONDUCTOR MFG3WORLDWIDE SEMICONDUCTOR MANUFA1
Top patents by PatentIndex Score
16 records- 0192US6037216AMethod for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene processVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Mar 14, 2000·95 cites·24 claims
- 0288US6022776AMethod of using silicon oxynitride to improve fabricating of DRAM contacts and landing padsWORLDWIDE SEMICONDUCTOR MANUFA·Filed 1999·Granted Feb 8, 2000·60 cites·3 claims
- 0386US6673683B1Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regionsTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Jan 6, 2004·42 cites·8 claims
- 0475US6338993B1Method to fabricate embedded DRAM with salicide logic cell structureWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Jan 15, 2002·34 cites·7 claims
- 0574US6080664AMethod for fabricating a high aspect ratio stacked contact holeVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Jun 27, 2000·48 cites·19 claims
- 0669US6124165AMethod for making openings in a passivation layer over polycide fuses using a single mask while forming reliable tungsten via plugs on DRAMsVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Sep 26, 2000·40 cites·28 claims
- 0763US6001717AMethod of making local interconnections for dynamic random access memory (DRAM) circuits with reduced contact resistance and reduced mask setVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Dec 14, 1999·30 cites·21 claims
- 0861US7071478B2System and method for passing particles on selected areas on a waferTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jul 4, 2006·4 cites·29 claims
- 0961US6876027B2Method of forming a metal-insulator-metal capacitor structure in a copper damascene process sequenceTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Apr 5, 2005·10 cites·8 claims
- 1056US6136646AMethod for manufacturing DRAM capacitorWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Oct 24, 2000·17 cites·14 claims
- 1151US6211091B1Self-aligned eetching processWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Apr 3, 2001·17 cites·18 claims
- 1251US6103623AMethod for fabricating a tungsten plug structure and an overlying interconnect metal structure without a tungsten etch back or CMP procedureVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Aug 15, 2000·21 cites·23 claims
- 1346US6074952AMethod for forming multi-level contactsVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Jun 13, 2000·13 cites·20 claims
- 1441US6096579AMethod for controlling the thickness of a passivation layer on a semiconductor deviceVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Aug 1, 2000·8 cites·20 claims
- 1529US2001001495A1Method for reducing contact resistanceFiled 1999·Application pending·0 cites
- 1625US6303955B1Dynamic random access memory with slanted active regionsWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Oct 16, 2001·3 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →