Inventor · disambiguated record
Philip Shiota
Also filed as: SHIOTA PHILIP · SHIOTA PHILIP S
11 granted patents·271 citations·filing 1979–2000
92Inventor score
Top patents by PatentIndex Score
11 records- 0183US4306916ACMOS P-Well selective implant methodAMERICAN MICRO SYST·Filed 1979·Granted Dec 22, 1981·44 cites·10 claims
- 0282US5272097AMethod for fabricating diodes for electrostatic discharge protection and voltage referencesSHIOTA PHILIP·Filed 1992·Granted Dec 21, 1993·55 cites·18 claims
- 0379US4455568AInsulation process for integrated circuitsAMERICAN MICRO SYST·Filed 1981·Granted Jun 19, 1984·45 cites·9 claims
- 0472US5591661AMethod for fabricating devices for electrostatic discharge protection and voltage references, and the resulting structuresFiled 1994·Granted Jan 7, 1997·37 cites·38 claims
- 0564US5086011AProcess for producing thin single crystal silicon islands on insulatorADVANCED MICRO DEVICES INC·Filed 1988·Granted Feb 4, 1992·30 cites·31 claims
- 0661US6445058B1Bipolar junction transistor incorporating integral field plateLEGERITY INC·Filed 2000·Granted Sep 3, 2002·10 cites·16 claims
- 0756US6437421B1Self-aligned dual-base semiconductor process and structure incorporating multiple bipolar device typesLEGERITY INC·Filed 2000·Granted Aug 20, 2002·8 cites·17 claims
- 0852US5426322ADiodes for electrostatic discharge protection and voltage referencesFiled 1993·Granted Jun 20, 1995·13 cites·3 claims
- 0943US4826779AIntegrated capacitor and method of fabricating sameTELEDYNE IND·Filed 1986·Granted May 2, 1989·11 cites·17 claims
- 1041US4835111AMethod of fabricating self-aligned zener diodeTELEDYNE IND·Filed 1987·Granted May 30, 1989·8 cites·14 claims
- 1139US4409726AMethod of making well regions for CMOS devicesSHIOTA PHILIP·Filed 1982·Granted Oct 18, 1983·10 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →