Inventor · disambiguated record
Ziyad S. Hakura
Also filed as: HAKURA ZIYAD · HAKURA ZIYAD S · HAKURA ZIYAD SAMI
88 granted patents·884 citations·filing 2000–2022
99Inventor score
Top patents by PatentIndex Score
88 records- 0198US8704826B1Primitive re-ordering between world-space and screen-space pipelines with buffer limited processingNVIDIA CORP·Filed 2013·Granted Apr 22, 2014·30 cites·20 claims
- 0297US6593925B1Parameterized animation compression methods and arrangementsMICROSOFT CORP·Filed 2000·Granted Jul 15, 2003·163 cites·85 claims
- 0396US8976195B1Generating clip state for a batch of verticesLINDHOLM JOHN ERIK·Filed 2009·Granted Mar 10, 2015·53 cites·26 claims
- 0495US8704836B1Distributing primitives to multiple rasterizersRHOADES JOHNNY S·Filed 2009·Granted Apr 22, 2014·55 cites·21 claims
- 0595US7248261B1Method and apparatus to accelerate rendering of shadow effects for computer-generated imagesNVIDIA CORP·Filed 2003·Granted Jul 24, 2007·82 cites·12 claims
- 0693US10120187B2Sub-frame scanout for latency reduction in virtual reality applicationsNVIDIA CORP·Filed 2016·Granted Nov 6, 2018·7 cites·20 claims
- 0793US8564616B1Cull before vertex attribute fetch and vertex lightingHAKURA ZIYAD S·Filed 2009·Granted Oct 22, 2013·14 cites·20 claims
- 0893US8542247B1Cull before vertex attribute fetch and vertex lightingHAKURA ZIYAD S·Filed 2009·Granted Sep 24, 2013·33 cites·22 claims
- 0993US7450120B1Apparatus, system, and method for Z-cullingNVIDIA CORP·Filed 2003·Granted Nov 11, 2008·70 cites·15 claims
- 1093US7053901B2System and method for accelerating a special purpose processorNVIDIA CORP·Filed 2003·Granted May 30, 2006·87 cites·28 claims
- 1192US7369126B1Method and apparatus to accelerate rendering of shadowsNVIDIA CORP·Filed 2006·Granted May 6, 2008·22 cites·10 claims
- 1291US7755624B1Apparatus, system, and method for Z-cullingNVIDIA CORP·Filed 2008·Granted Jul 13, 2010·21 cites·10 claims
- 1388US9639367B2Managing event count reports in a tile-based architectureNVIDIA CORP·Filed 2013·Granted May 2, 2017·4 cites·20 claims
- 1488US9612839B2Higher accuracy Z-culling in a tile-based architectureNVIDIA CORP·Filed 2013·Granted Apr 4, 2017·4 cites·21 claims
- 1588US8817031B2Distributed stream output in a parallel processing unitHAKURA ZIYAD S·Filed 2010·Granted Aug 26, 2014·11 cites·20 claims
- 1687US9830741B2Setting downstream render state in an upstream shaderNVIDIA CORP·Filed 2012·Granted Nov 28, 2017·9 cites·22 claims
- 1787US8941653B2Order-preserving distributed rasterizerNVIDIA CORP·Filed 2013·Granted Jan 27, 2015·8 cites·20 claims
- 1886US8704835B1Distributed clip, cull, viewport transform and perspective correctionHAKURA ZIYAD S·Filed 2009·Granted Apr 22, 2014·6 cites·19 claims
- 1986US7765500B2Automated generation of theoretical performance analysis based upon workload and design configurationNVIDIA CORP·Filed 2007·Granted Jul 27, 2010·18 cites·22 claims
- 2085US9710874B2Mid-primitive graphics execution preemptionNVIDIA CORP·Filed 2012·Granted Jul 18, 2017·8 cites·23 claims
- 2185US8692829B2Calculation of plane equations after determination of Z-buffer visibilityHAKURA ZIYAD S·Filed 2010·Granted Apr 8, 2014·9 cites·17 claims
- 2284US8947444B1Distributed vertex attribute fetchHAKURA ZIYAD S·Filed 2008·Granted Feb 3, 2015·13 cites·24 claims
- 2383US8749564B2Barrier commands in a cache tiling architectureNVIDIA CORP·Filed 2013·Granted Jun 10, 2014·1 cites·23 claims
- 2482US9734548B2Caching of adaptively sized cache tiles in a unified L2 cache with surface compressionNVIDIA CORP·Filed 2013·Granted Aug 15, 2017·6 cites·21 claims
- 2582US9311097B2Managing per-tile event count reports in a tile-based architectureNVIDIA CORP·Filed 2013·Granted Apr 12, 2016·2 cites·20 claims
- 2681US9536341B1Distributing primitives to multiple rasterizersRHOADES JOHNNY S·Filed 2009·Granted Jan 3, 2017·12 cites·21 claims
- 2780US9336002B2Data structures for efficient tiled renderingNVIDIA CORP·Filed 2013·Granted May 10, 2016·2 cites·20 claims
- 2880US8310482B1Distributed calculation of plane equationsHAKURA ZIYAD S·Filed 2008·Granted Nov 13, 2012·9 cites·19 claims
- 2979US10430989B2Multi-pass rendering in a screen space pipelineNVIDIA CORP·Filed 2015·Granted Oct 1, 2019·3 cites·18 claims
- 3079US10068366B2Stereo multi-projection implemented using a graphics processing pipelineNVIDIA CORP·Filed 2016·Granted Sep 4, 2018·3 cites·20 claims
- 3179US10032245B2Techniques for maintaining atomicity and ordering for pixel shader operationsNVIDIA CORP·Filed 2015·Granted Jul 24, 2018·3 cites·22 claims
- 3277US10853994B1Rendering scenes using a combination of raytracing and rasterizationNVIDIA CORP·Filed 2019·Granted Dec 1, 2020·2 cites·22 claims
- 3377US10055806B2Techniques for maintaining atomicity and ordering for pixel shader operationsNVIDIA CORP·Filed 2015·Granted Aug 21, 2018·2 cites·22 claims
- 3476US10909739B2Techniques for representing and processing geometry within an expanded graphics processing pipelineNVIDIA CORP·Filed 2018·Granted Feb 2, 2021·2 cites·22 claims
- 3576US8941676B2On-chip anti-alias resolve in a cache tiling architectureNVIDIA CORP·Filed 2013·Granted Jan 27, 2015·1 cites·20 claims
- 3675US11107176B2Scheduling cache traffic in a tile-based architectureNVIDIA CORP·Filed 2013·Granted Aug 31, 2021·1 cites·17 claims
- 3775US10019776B2Techniques for maintaining atomicity and ordering for pixel shader operationsNVIDIA CORP·Filed 2015·Granted Jul 10, 2018·2 cites·22 claims
- 3875US9639366B2Techniques for managing graphics processing resources in a tile-based architectureNVIDIA CORP·Filed 2013·Granted May 2, 2017·1 cites·20 claims
- 3975US7342590B1Screen compressionNVIDIA CORP·Filed 2003·Granted Mar 11, 2008·12 cites·20 claims
- 4074US9747661B2Consistent vertex snapping for variable resolution renderingNVIDIA CORP·Filed 2016·Granted Aug 29, 2017·2 cites·18 claims
- 4173US9779533B2Hierarchical tiled cachingNVIDIA CORP·Filed 2014·Granted Oct 3, 2017·3 cites·25 claims
- 4273US9418616B2Technique for storing shared verticesNVIDIA CORP·Filed 2012·Granted Aug 16, 2016·3 cites·20 claims
- 4373US8917271B2Redistribution of generated geometric primitivesRHOADES JOHNNY S·Filed 2010·Granted Dec 23, 2014·4 cites·24 claims
- 4473US8810592B2Vertex attribute buffer for inline immediate attributes and constantsHAKURA ZIYAD S·Filed 2010·Granted Aug 19, 2014·5 cites·17 claims
- 4573US7441087B2System, apparatus and method for issuing predictions from an inventory to access a memoryNVIDIA CORP·Filed 2004·Granted Oct 21, 2008·22 cites·21 claims
- 4672US10438314B2Two-pass cache tile processing for visibility testing in a tile-based architectureNVIDIA CORP·Filed 2018·Granted Oct 8, 2019·1 cites·20 claims
- 4772US9501847B1Parallel line stipple computationPURCELL TIMOTHY JOHN·Filed 2009·Granted Nov 22, 2016·6 cites·20 claims
- 4871US9792122B2Heuristics for improving performance in a tile based architectureNVIDIA CORP·Filed 2013·Granted Oct 17, 2017·0 cites·22 claims
- 4971US7206902B2System, apparatus and method for predicting accesses to a memoryNVIDIA CORP·Filed 2004·Granted Apr 17, 2007·17 cites·28 claims
- 5070US11016802B2Techniques for ordering atomic operationsNVIDIA CORP·Filed 2018·Granted May 25, 2021·1 cites·21 claims
Showing the top 50 of 88 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →