Inventor · disambiguated record
Bibiche M. Geuskens
Also filed as: GEUSKENS BIBICHE · GEUSKENS BIBICHE M
10 granted patents·49 citations·filing 2007–2019
87Inventor score
Technology areasG11C
Top patents by PatentIndex Score
10 records- 0194US9299395B2Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocksKULKARNI JAYDEEP P·Filed 2012·Granted Mar 29, 2016·18 cites·19 claims
- 0287US9153304B2Apparatus for reducing write minimum supply voltage for memoryKULKARNI JAYDEEP P·Filed 2012·Granted Oct 6, 2015·10 cites·33 claims
- 0376US9633716B2Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocksINTEL CORP·Filed 2016·Granted Apr 25, 2017·3 cites·22 claims
- 0473US8467263B2Memory write operation methods and circuitsKULKARNI JAYDEEP P·Filed 2010·Granted Jun 18, 2013·5 cites·11 claims
- 0569US9627039B2Apparatus for reducing write minimum supply voltage for memoryINTEL CORP·Filed 2015·Granted Apr 18, 2017·2 cites·20 claims
- 0666US8094505B2Method and system to lower the minimum operating voltage of a memory arrayKHELLAH MUHAMMAD M·Filed 2009·Granted Jan 10, 2012·6 cites·7 claims
- 0752US10984855B2Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocksINTEL CORP·Filed 2019·Granted Apr 20, 2021·0 cites·23 claims
- 0850US10217509B2Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocksINTEL CORP·Filed 2017·Granted Feb 26, 2019·0 cites·19 claims
- 0950US8868836B2Reducing minimum operating voltage through hybrid cache designKHELLAH MUHAMMAD M·Filed 2007·Granted Oct 21, 2014·2 cites·19 claims
- 1047US8456923B2Register file circuits with P-type evaluationGEUSKENS BIBICHE·Filed 2008·Granted Jun 4, 2013·3 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →