Inventor · disambiguated record
Abhijeet Kolpekwar
Also filed as: KOLPEKWAR ABHIJEET · KOLPEKWAR ABHIJEET S
14 granted patents·1 pending application·128 citations·filing 2004–2020
92Inventor score
Technology areasG06F
Files withCADENCE DESIGN SYSTEMS INC8CHETPUT CHANDRASHEKAR L3KOLPEKWAR ABHIJEET3SIEMENS IND SOFTWARE INC1
Top patents by PatentIndex Score
15 records- 0191US8296699B1Method and system for supporting both analog and digital signal traffic on a single hierarchical connection for mixed-signal verificationCHETPUT CHANDRASHEKAR L·Filed 2010·Granted Oct 23, 2012·21 cites·36 claims
- 0285US8234617B2Method and system for re-using digital assertions in a mixed signal designCHETPUT CHANDRASHEKAR L·Filed 2009·Granted Jul 31, 2012·16 cites·30 claims
- 0384US8732630B1Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description languageCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted May 20, 2014·9 cites·32 claims
- 0484US7797659B2Analog/digital partitioning of circuit designs for simulationCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Sep 14, 2010·13 cites·11 claims
- 0581US9501592B1Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description languageCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Nov 22, 2016·7 cites·29 claims
- 0680US8255191B1Using real value models in simulation of analog and mixed-signal systemsKOLPEKWAR ABHIJEET·Filed 2009·Granted Aug 28, 2012·12 cites·28 claims
- 0779US8949753B1Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description languageCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Feb 3, 2015·6 cites·31 claims
- 0877US7523424B2Method and system for representing analog connectivity in hardware description language designsCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Apr 21, 2009·13 cites·24 claims
- 0975US9058440B1Method and mechanism for verifying and simulating power aware mixed-signal electronic designsKOLPEKWAR ABHIJEET·Filed 2009·Granted Jun 16, 2015·8 cites·29 claims
- 1075US8448116B2Analog/digital partitioning of circuit designs for simulationCHETPUT CHANDRASHEKAR L·Filed 2010·Granted May 21, 2013·4 cites·5 claims
- 1170US7979262B1Method for verifying connectivity of electrical circuit componentsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jul 12, 2011·6 cites·50 claims
- 1264US8504346B1Method and mechanism for performing mixed-signal simulation of electronic designs having complex digital signal types or modelsKOLPEKWAR ABHIJEET·Filed 2009·Granted Aug 6, 2013·3 cites·38 claims
- 1362US7251795B2Connecting verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal designCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Jul 31, 2007·10 cites·18 claims
- 1453US8640073B2Analog/digital partitioning of circuit designs for simulationCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Jan 28, 2014·0 cites·6 claims
- 1540US2023315964A1Design aware adaptive mixed-signal simulationSIEMENS IND SOFTWARE INC·Filed 2020·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →