Inventor · disambiguated record
Elie Awad
Also filed as: AWAD ELIE
12 granted patents·1 pending application·82 citations·filing 2003–2009
90Inventor score
Top patents by PatentIndex Score
13 records- 0191US7498673B2Heatplates for heatsink attachment for semiconductor chipsIBM·Filed 2006·Granted Mar 3, 2009·21 cites·14 claims
- 0278US7834444B2Heatplates for heatsink attachment for semiconductor chipsIBM·Filed 2009·Granted Nov 16, 2010·7 cites·20 claims
- 0376US6815806B1Asymmetric partially-etched leads for finer pitch semiconductor chip packageIBM·Filed 2003·Granted Nov 9, 2004·21 cites·9 claims
- 0469US6894382B1Optimized electronic packageIBM·Filed 2004·Granted May 17, 2005·16 cites·25 claims
- 0568US7666712B2Design of BEOL patterns to reduce the stresses on structures below chip bondpadsIBM·Filed 2008·Granted Feb 23, 2010·3 cites·8 claims
- 0659US7489038B2Design of BEOL patterns to reduce the stresses on structures below chip bondpadsIBM·Filed 2005·Granted Feb 10, 2009·1 cites·11 claims
- 0756US7595681B2Method and apparatus for compensating for variances of a buried resistor in an integrated circuitIBM·Filed 2006·Granted Sep 29, 2009·4 cites·5 claims
- 0853US8341428B2System and method to protect computing systemsAWAD ELIE·Filed 2007·Granted Dec 25, 2012·2 cites·25 claims
- 0950US7071559B2Design of beol patterns to reduce the stresses on structures below chip bondpadsIBM·Filed 2004·Granted Jul 4, 2006·3 cites·2 claims
- 1049US7251872B2Method for forming a chip packageIBM·Filed 2004·Granted Aug 7, 2007·3 cites·4 claims
- 1145US7962322B2Design structure for compensating for variances of a buried resistor in an integrated circuitIBM·Filed 2008·Granted Jun 14, 2011·1 cites·8 claims
- 1243US2008320423A1System and method to protect computing systemsIBM·Filed 2007·Application pending·0 cites
- 1336US7886237B2Method of generating a functional design structureIBM·Filed 2008·Granted Feb 8, 2011·0 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →