Inventor · disambiguated record
Robert P. Colwell
Also filed as: COLWELL ROBERT P
40 granted patents·2,965 citations·filing 1987–1999
99Inventor score
Technology areasG06F
Top patents by PatentIndex Score
40 records- 0196US5721855AMethod for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder bufferINTEL CORP·Filed 1996·Granted Feb 24, 1998·335 cites·23 claims
- 0294US4833599AHierarchical priority branch handling for parallel execution in a parallel processorMULTIFLOW COMPUTER INC·Filed 1987·Granted May 23, 1989·233 cites·9 claims
- 0390US5179680AInstruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatusDIGITAL EQUIPMENT CORP·Filed 1991·Granted Jan 12, 1993·155 cites·3 claims
- 0489US4920477AVirtual address table look aside buffer miss recovery method and apparatusMULTIFLOW COMPUTER INC·Filed 1987·Granted Apr 24, 1990·120 cites·6 claims
- 0588US5778245AMethod and apparatus for dynamic allocation of multiple buffers in a processorINTEL CORP·Filed 1994·Granted Jul 7, 1998·131 cites·22 claims
- 0688US5057837AInstruction storage method with a compressed format using a mask wordDIGITAL EQUIPMENT CORP·Filed 1990·Granted Oct 15, 1991·139 cites·9 claims
- 0786US6047369AFlag renaming and flag masks within register alias tableINTEL CORP·Filed 1994·Granted Apr 4, 2000·122 cites·48 claims
- 0885US5627985ASpeculative and committed resource files in an out-of-order processorINTEL CORP·Filed 1994·Granted May 6, 1997·112 cites·33 claims
- 0981US6079014AProcessor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural stateINTEL CORP·Filed 1997·Granted Jun 20, 2000·101 cites·23 claims
- 1081US5584038AEntry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversedINTEL CORP·Filed 1996·Granted Dec 10, 1996·89 cites·8 claims
- 1181US5446912APartial width stalls within register alias tableINTEL CORP·Filed 1993·Granted Aug 29, 1995·84 cites·34 claims
- 1280US6349380B1Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessorINTEL CORP·Filed 1999·Granted Feb 19, 2002·91 cites·18 claims
- 1380US5499352AFloating point register alias table FXCH and retirement floating point register arrayINTEL CORP·Filed 1993·Granted Mar 12, 1996·73 cites·51 claims
- 1478US5687338AMethod and apparatus for maintaining a macro instruction for refetching in a pipelined processorINTEL CORP·Filed 1995·Granted Nov 11, 1997·81 cites·6 claims
- 1576US5809271AMethod and apparatus for changing flow of control in a processorINTEL CORP·Filed 1995·Granted Sep 15, 1998·63 cites·7 claims
- 1676US5729728AMethod and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessorINTEL CORP·Filed 1996·Granted Mar 17, 1998·67 cites·49 claims
- 1776US5561814AMethods and apparatus for determining memory operating characteristics for given memory locations via assigned address rangesINTEL CORP·Filed 1993·Granted Oct 1, 1996·59 cites·38 claims
- 1875US5471633AIdiom recognizer within a register alias tableINTEL CORP·Filed 1994·Granted Nov 28, 1995·67 cites·56 claims
- 1975US5452426ACoordinating speculative and committed state register source data and immediate source data in a processorINTEL CORP·Filed 1994·Granted Sep 19, 1995·66 cites·44 claims
- 2070US5974523AMechanism for efficiently overlapping multiple operand types in a microprocessorINTEL CORP·Filed 1996·Granted Oct 26, 1999·40 cites·27 claims
- 2170US5546597AReady selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction executionINTEL CORP·Filed 1994·Granted Aug 13, 1996·51 cites·22 claims
- 2269US5524262AApparatus and method for renaming registers in a processor and resolving data dependencies thereofINTEL CORP·Filed 1995·Granted Jun 4, 1996·48 cites·5 claims
- 2368US5613132AInteger and floating point register alias table within processor deviceINTEL CORP·Filed 1993·Granted Mar 18, 1997·53 cites·30 claims
- 2468US5564056AMethod and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renamingINTEL CORP·Filed 1994·Granted Oct 8, 1996·41 cites·10 claims
- 2568US5564111AMethod and apparatus for implementing a non-blocking translation lookaside bufferINTEL CORP·Filed 1994·Granted Oct 8, 1996·46 cites·18 claims
- 2665US5574942AHybrid execution unit for complex microprocessorINTEL CORP·Filed 1996·Granted Nov 12, 1996·54 cites·29 claims
- 2765US5307506AHigh bandwidth multiple computer bus apparatusDIGITAL EQUIPMENT CORP·Filed 1992·Granted Apr 26, 1994·51 cites·13 claims
- 2863US5615385AMethod and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renamingINTEL CORP·Filed 1995·Granted Mar 25, 1997·37 cites·6 claims
- 2962US5778407AMethods and apparatus for determining operating characteristics of a memory element based on its physical locationINTEL CORP·Filed 1996·Granted Jul 7, 1998·35 cites·7 claims
- 3061US5751986AComputer system with self-consistent ordering mechanismINTEL CORP·Filed 1997·Granted May 12, 1998·39 cites·34 claims
- 3161US5727176AData processor with circuitry for handling pointers associated with a register exchange operationINTEL CORP·Filed 1996·Granted Mar 10, 1998·36 cites·8 claims
- 3260US5584037AEntry allocation in a circular bufferINTEL CORP·Filed 1995·Granted Dec 10, 1996·34 cites·3 claims
- 3359US5987600AException handling in a processor that performs speculative out-of-order instruction executionINTEL CORP·Filed 1997·Granted Nov 16, 1999·35 cites·16 claims
- 3458US6079033ASelf-monitoring distributed hardware systemsINTEL CORP·Filed 1997·Granted Jun 20, 2000·33 cites·16 claims
- 3558US5548776AN-wide bypass for data dependencies within register alias tableINTEL CORP·Filed 1993·Granted Aug 20, 1996·27 cites·29 claims
- 3657US5604878AMethod and apparatus for avoiding writeback conflicts between execution units sharing a common writeback pathINTEL CORP·Filed 1995·Granted Feb 18, 1997·33 cites·24 claims
- 3755US6101597AMethod and apparatus for maximum throughput scheduling of dependent operations in a pipelined processorINTEL CORP·Filed 1993·Granted Aug 8, 2000·27 cites·42 claims
- 3852US5497493AHigh byte right-shift apparatus with a register alias tableINTEL CORP·Filed 1993·Granted Mar 5, 1996·23 cites·52 claims
- 3947US5826094ARegister alias table update to indicate architecturally visible stateINTEL CORP·Filed 1996·Granted Oct 20, 1998·20 cites·40 claims
- 4042US5913050AMethod and apparatus for providing address-size backward compatibility in a processor using segmented memoryINTEL CORP·Filed 1996·Granted Jun 15, 1999·14 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →