Inventor · disambiguated record
Keith E. Zawadzki
Also filed as: ZAWADZKI KEITH · ZAWADZKI KEITH E · ZAWADZKI KEITH EDWARD
6 granted patents·14 pending applications·186 citations·filing 2003–2024
81Inventor score
Top patents by PatentIndex Score
20 records- 0196US7598142B2CMOS device with dual-epi channels and self-aligned contactsRANADE PUSHKAR·Filed 2007·Granted Oct 6, 2009·137 cites·7 claims
- 0295US7691752B2Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed therebyINTEL CORP·Filed 2007·Granted Apr 6, 2010·45 cites·12 claims
- 0384US12014996B2Moisture hermetic guard ring for semiconductor on insulator devicesINTEL CORP·Filed 2020·Granted Jun 18, 2024·2 cites·12 claims
- 0474US12406945B2Moisture hermetic guard ring for semiconductor on insulator devicesINTEL CORP·Filed 2024·Granted Sep 2, 2025·0 cites·20 claims
- 0564US8394687B2Ultra-abrupt semiconductor junction profileRANADE PUSHKAR·Filed 2007·Granted Mar 12, 2013·2 cites·9 claims
- 0659US2024347590A1Methods and apparatus to reduce stress in integrated circuit packagesINTEL CORP·Filed 2024·Application pending·0 cites
- 0755US12438102B2Hermetic barrier surrounding a plurality of diesINTEL CORP·Filed 2021·Granted Oct 7, 2025·0 cites·20 claims
- 0853US2025112167A1Semiconductor design lithographic seam implementation methodology for advanced technologiesINTEL CORP·Filed 2023·Application pending·0 cites
- 0952US2025006653A1Fiducials with associated low-density metal zonesINTEL CORP·Filed 2023·Application pending·0 cites
- 1052US2025006652A1Fiducials with underlying dummy metallization for integrated circuit device alignmentINTEL CORP·Filed 2023·Application pending·0 cites
- 1148US2024363490A1Through-silicon via dieINTEL CORP·Filed 2023·Application pending·0 cites
- 1247US2009011581A1Carbon controlled fixed charge processWEBER CORY E·Filed 2008·Application pending·0 cites
- 1347US2023197538A1Hermetic seal for transistors with metal on both sidesINTEL CORP·Filed 2021·Application pending·0 cites
- 1446US2007034945A1PMOS transistor strain optimization with raised junction regionsBOHR MARK T·Filed 2006·Application pending·0 cites
- 1546US2024145383A1Integrated ring structuresINTEL CORP·Filed 2022·Application pending·0 cites
- 1644US2008237741A1Methods of forming improved epi fill on narrow isolation bounded source/drain regions and structures formed therebyRANADE PUSHKAR·Filed 2007·Application pending·0 cites
- 1742US2007077739A1Carbon controlled fixed charge processWEBER CORY E·Filed 2005·Application pending·0 cites
- 1842US2009315120A1Raised facet- and non-facet 3d source/drain contacts in mosfetsSHIFREN LUCIAN·Filed 2008·Application pending·0 cites
- 1940US2009085097A1Methods of forming nitride stressing layer for replacement metal gate and structures formed therebySHIFREN LUCIAN·Filed 2007·Application pending·0 cites
- 2037US2004262683A1PMOS transistor strain optimization with raised junction regionsFiled 2003·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Keith E. Zawadzki files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →