Inventor · disambiguated record
Ho Dai Truong
Also filed as: TRUONG HO D · TRUONG HO DAI
13 granted patents·312 citations·filing 1982–2008
94Inventor score
Files withSEIKO EPSON CORP8SAMSUNG ELECTRONICS CO LTD2SEIKO EPSON CORP OF TOKYO JAPA1SMOS SYSTEMS INC1XEROX CORP1
Top patents by PatentIndex Score
13 records- 0195US5444405AClock generator with programmable non-overlapping clock edge capabilitySEIKO EPSON CORP·Filed 1994·Granted Aug 22, 1995·55 cites·2 claims
- 0287US6900682B2Clock generator with programmable non-overlapping-clock-edge capabilitySEIKO EPSON CORP·Filed 2003·Granted May 31, 2005·19 cites·10 claims
- 0385US6323711B2Clock generator with programmable non-overlapping-clock-edge-capabilitySEIKO EPSON CORP·Filed 2000·Granted Nov 27, 2001·18 cites·7 claims
- 0485US5214320ASystem and method for reducing ground bounce in integrated circuit output buffersSMOS SYSTEMS INC·Filed 1992·Granted May 25, 1993·57 cites·11 claims
- 0585US4733108AOn-chip bias generatorXEROX CORP·Filed 1982·Granted Mar 22, 1988·42 cites·4 claims
- 0684US6163194AIntegrated circuit with hardware-based programmable non-overlapping-clock-edge capabilitySEIKO EPSON CORP·Filed 1999·Granted Dec 19, 2000·26 cites·7 claims
- 0780US6489826B2Clock generator with programmable non-overlapping clock-edge capabilitySEIKO EPSON CORP·Filed 2001·Granted Dec 3, 2002·13 cites·24 claims
- 0877US6653881B2Clock generator with programmable non-overlapping-clock-edge capabilitySEIKO EPSON CORP·Filed 2002·Granted Nov 25, 2003·11 cites·14 claims
- 0975US7642832B2Clock generator with programmable non-overlapping-clock-edge capabilitySEIKO EPSON CORP·Filed 2008·Granted Jan 5, 2010·4 cites·11 claims
- 1072US5877636ASynchronous multiplexer for clock signalsSAMSUNG ELECTRONICS CO LTD·Filed 1996·Granted Mar 2, 1999·32 cites·34 claims
- 1170US5966037AMethod for manufacturing an integrated circuit with programmable non-overlapping-clock-edge capabilitySEIKO EPSON CORP OF TOKYO JAPA·Filed 1997·Granted Oct 12, 1999·15 cites·4 claims
- 1264US7352222B2Clock generator with programmable non-overlapping-clock-edge capabilitySEIKO EPSON CORP·Filed 2005·Granted Apr 1, 2008·2 cites·6 claims
- 1352US6031982ALayout design of integrated circuit, especially datapath circuitry, using function cells formed with fixed basic cell and configurable interconnect networksSAMSUNG ELECTRONICS CO LTD·Filed 1996·Granted Feb 29, 2000·18 cites·56 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →