Inventor · disambiguated record
Valeriy B. Kudryavtsev
Also filed as: KUDRYAVTSEV VALERIY B
20 granted patents·1,663 citations·filing 1995–2003
97Inventor score
Files withLSI LOGIC CORP20
Top patents by PatentIndex Score
20 records- 0198US5777360AHexagonal field programmable gate array architectureLSI LOGIC CORP·Filed 1995·Granted Jul 7, 1998·338 cites·49 claims
- 0296US6407434B1Hexagonal architectureLSI LOGIC CORP·Filed 1995·Granted Jun 18, 2002·245 cites·4 claims
- 0396US5650653AMicroelectronic integrated circuit including triangular CMOS "nand" gate deviceLSI LOGIC CORP·Filed 1995·Granted Jul 22, 1997·175 cites·47 claims
- 0494US5811863ATransistors having dynamically adjustable characteristicsLSI LOGIC CORP·Filed 1995·Granted Sep 22, 1998·202 cites·47 claims
- 0593US5973376AArchitecture having diamond shaped or parallelogram shaped cellsLSI LOGIC CORP·Filed 1995·Granted Oct 26, 1999·157 cites·9 claims
- 0693US5742086AHexagonal DRAM arrayLSI LOGIC CORP·Filed 1995·Granted Apr 21, 1998·162 cites·40 claims
- 0780US6134702APhysical design automation system and process for designing integrated circuit chips using multiway partitioning with constraintsLSI LOGIC CORP·Filed 1997·Granted Oct 17, 2000·90 cites·22 claims
- 0873US5661663APhysical design automation system and method using hierarchical clusterization and placement improvement based on complete re-placement of cell clustersLSI LOGIC CORP·Filed 1995·Granted Aug 26, 1997·66 cites·41 claims
- 0972US5699265APhysical design automation system and process for designing integrated circuit chips using multiway partitioning with constraintsLSI LOGIC CORP·Filed 1995·Granted Dec 16, 1997·63 cites·22 claims
- 1062US6097073ATriangular semiconductor or gateLSI LOGIC CORP·Filed 1995·Granted Aug 1, 2000·27 cites·26 claims
- 1156US5909376APhysical design automation system and process for designing integrated circuit chips using highly parallel sieve optimization with multiple "jiggles"LSI LOGIC CORP·Filed 1995·Granted Jun 1, 1999·32 cites·32 claims
- 1255US7103865B2Process and apparatus for placement of megacells in ICs designLSI LOGIC CORP·Filed 2003·Granted Sep 5, 2006·4 cites·18 claims
- 1353US5864165ATriangular semiconductor NAND gateLSI LOGIC CORP·Filed 1995·Granted Jan 26, 1999·18 cites·95 claims
- 1451US5835378AComputer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chipLSI LOGIC CORP·Filed 1995·Granted Nov 10, 1998·24 cites·30 claims
- 1551US5801422AHexagonal SRAM architectureLSI LOGIC CORP·Filed 1995·Granted Sep 1, 1998·16 cites·67 claims
- 1647US5838585APhysical design automation system and method using monotonically improving linear clusterizationLSI LOGIC CORP·Filed 1997·Granted Nov 17, 1998·19 cites·35 claims
- 1744US5834821ATriangular semiconductor "AND" gate deviceLSI LOGIC CORP·Filed 1995·Granted Nov 10, 1998·11 cites·37 claims
- 1842US5654563AMicroelectronic integrated circuit including triangular semiconductor "or"gLSI LOGIC CORP·Filed 1995·Granted Aug 5, 1997·7 cites·39 claims
- 1940US5631581AMicroelectronic integrated circuit including triangular semiconductor "and" gate deviceLSI LOGIC CORP·Filed 1995·Granted May 20, 1997·6 cites·38 claims
- 2030US5784287APhysical design automation system and process for designing integrated circuit chips using generalized assignmentLSI LOGIC CORP·Filed 1995·Granted Jul 21, 1998·1 cites·32 claims
Join the waitlist — get patent alerts
Get an alert when Valeriy B. Kudryavtsev files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →