Inventor · disambiguated record
Jose M. Nunez
Also filed as: NUNEZ JOSE M · NUNEZ JOSE MELANIO
20 granted patents·518 citations·filing 1996–2014
96Inventor score
Top patents by PatentIndex Score
20 records- 0190US8300464B2Method and circuit for calibrating data capture in a memory controllerWELKER JAMES A·Filed 2010·Granted Oct 30, 2012·18 cites·20 claims
- 0287US6119204AData processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serializationIBM·Filed 1998·Granted Sep 12, 2000·143 cites·16 claims
- 0382US6898682B2Automatic READ latency calculation without software intervention for a source-synchronous interfaceFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted May 24, 2005·40 cites·12 claims
- 0476US7240041B2Network message processing using inverse pattern matchingFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Jul 3, 2007·23 cites·30 claims
- 0576US6937961B2Performance monitor and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Aug 30, 2005·26 cites·22 claims
- 0670US9423972B2Error recovery in a data processing system which implements partial writesFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Aug 23, 2016·2 cites·20 claims
- 0766US6615323B1Optimizing pipelined snoop processingFiled 1999·Granted Sep 2, 2003·49 cites·16 claims
- 0862US7181638B2Method and apparatus for skewing data with respect to command on a DDR interfaceFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Feb 20, 2007·10 cites·38 claims
- 0961US7613775B2Network message filtering using hashing and pattern matchingFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Nov 3, 2009·7 cites·52 claims
- 1060US5835946AHigh performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizationsIBM·Filed 1996·Granted Nov 10, 1998·42 cites·7 claims
- 1159US6272601B1Critical word forwarding in a multiprocessor systemIBM·Filed 1999·Granted Aug 7, 2001·34 cites·20 claims
- 1256US6460133B1Queue resource tracking in a multiprocessor systemIBM·Filed 1999·Granted Oct 1, 2002·29 cites·20 claims
- 1354US6249845B1Method for supporting cache control instructions within a coherency granuleIBM·Filed 1998·Granted Jun 19, 2001·27 cites·19 claims
- 1446US6430658B1Local cache-to-cache transfers in a multiprocessor systemIBM·Filed 1999·Granted Aug 6, 2002·18 cites·20 claims
- 1546US6272604B1Contingent response apparatus and method for maintaining cache coherencyIBM·Filed 1999·Granted Aug 7, 2001·21 cites·30 claims
- 1641US9195625B2Interconnect controller for a data processing device with transaction tag locking and method thereforIKONOMOPOULOS GUS P·Filed 2009·Granted Nov 24, 2015·0 cites·20 claims
- 1741US6847990B2Data transfer unit with support for multiple coherency granulesFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Jan 25, 2005·0 cites·26 claims
- 1840US6389516B1Intervention ordering in a multiprocessor systemIBM·Filed 1999·Granted May 14, 2002·14 cites·20 claims
- 1937US6275906B1Coherency maintenance in a multiprocessor systemIBM·Filed 1999·Granted Aug 14, 2001·10 cites·22 claims
- 2033US6338121B1Data source arbitration in a multiprocessor systemIBM·Filed 1999·Granted Jan 8, 2002·5 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →