Inventor · disambiguated record
Sudesh Chandra Srivastava
Also filed as: SRIVASTAVA SUDESH CHANDRA
4 granted patents·1 pending application·3 citations·filing 2014–2023
59Inventor score
Top patents by PatentIndex Score
5 records- 0168US9319045B1Method and apparatus for reducing gate leakage of low threshold transistors during low power mode in a multi-power-domain chipTEXAS INSTRUMENTS INC·Filed 2014·Granted Apr 19, 2016·3 cites·20 claims
- 0254US11631454B2Methods and apparatus for reduced area control register circuitTEXAS INSTRUMENTS INC·Filed 2020·Granted Apr 18, 2023·0 cites·20 claims
- 0349US2025072110A1Domain merger cell to abut power domains for chip area reductionQUALCOMM INC·Filed 2023·Application pending·0 cites
- 0441US9705481B1Area-optimized retention flop implementationTEXAS INSTRUMENTS INC·Filed 2015·Granted Jul 11, 2017·0 cites·18 claims
- 0537US10559351B2Methods and apparatus for reduced area control register circuitTEXAS INSTRUMENTS INC·Filed 2017·Granted Feb 11, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →