Inventor · disambiguated record
Muriel Martinez
Also filed as: MARTINEZ MURIEL
7 granted patents·1 pending application·95 citations·filing 2003–2009
85Inventor score
Top patents by PatentIndex Score
8 records- 0189US7406994B2Substrate layer cutting device and methodSOITEC SILICON ON INSULATOR·Filed 2007·Granted Aug 5, 2008·17 cites·19 claims
- 0282US6858517B2Methods of producing a heterogeneous semiconductor structureSOITEC SILICON ON INSULATOR·Filed 2004·Granted Feb 22, 2005·31 cites·19 claims
- 0380US6989314B2Semiconductor structure and method of making sameSOITEC SILICON ON INSULATOR·Filed 2004·Granted Jan 24, 2006·27 cites·23 claims
- 0467US7718534B2Planarization of a heteroepitaxial layerSOITEC SILICON ON INSULATOR·Filed 2006·Granted May 18, 2010·4 cites·20 claims
- 0566US7189304B2Substrate layer cutting device and methodSOITEC SILICON ON INSULATOR·Filed 2003·Granted Mar 13, 2007·10 cites·22 claims
- 0663US8304345B2Germanium layer polishingMARTINEZ MURIEL·Filed 2009·Granted Nov 6, 2012·5 cites·18 claims
- 0759US7391094B2Semiconductor structure and method of making sameSOITEC SILICON ON INSULATOR·Filed 2005·Granted Jun 24, 2008·1 cites·13 claims
- 0838US2011117740A1Method for polishing heterostructuresSOITEC SILICON ON INSULATOR·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →