Inventor · disambiguated record
Michael Scheppler
Also filed as: SCHEPPLER MICHAEL
9 granted patents·2 pending applications·218 citations·filing 2004–2013
88Inventor score
Top patents by PatentIndex Score
11 records- 0196US7755110B2Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zoneINFINEON TECHNOLOGIES AG·Filed 2005·Granted Jul 13, 2010·136 cites·24 claims
- 0293US7492187B2Circuit arrangement for supplying configuration data in FPGA devicesINFINEON TECHNOLOGIES AG·Filed 2006·Granted Feb 17, 2009·28 cites·23 claims
- 0381US7199618B2Logic circuit arrangementINFINEON TECHNOLOGIES AG·Filed 2004·Granted Apr 3, 2007·26 cites·22 claims
- 0480US7864579B2Integrated circuits having a controller to control a read operation and methods for operating the sameQIMONDA AG·Filed 2008·Granted Jan 4, 2011·15 cites·4 claims
- 0577US8589765B1Memory read-outQIMONDA AG·Filed 2013·Granted Nov 19, 2013·5 cites·20 claims
- 0669US7348795B2Configurable logic component without a local configuration memory and with a parallel configuration busINFINEON TECHNOLOGIES AG·Filed 2005·Granted Mar 25, 2008·6 cites·13 claims
- 0741US8533563B2Memory read-outSCHEPPLER MICHAEL·Filed 2008·Granted Sep 10, 2013·0 cites·3 claims
- 0841US7439765B2Mask-programmable logic macro and method for programming a logic macroINFINEON TECHNOLOGIES AG·Filed 2006·Granted Oct 21, 2008·0 cites·20 claims
- 0941US7323904B2Look-up tableINFINEON TECHNOLOGIES AG·Filed 2005·Granted Jan 29, 2008·2 cites·12 claims
- 1041US2010308863A1Architecture of Function Blocks and Wirings in a Structured ASIC and Configurable Driver Cell of a Logic Cell ZoneGLIESE JOERG·Filed 2010·Application pending·0 cites
- 1138US2009282308A1Memory Cell Arrangement and Method for Reading State Information From a Memory Cell Bypassing an Error Detection CircuitGUTSCHE JAN·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →