Inventor · disambiguated record
Bang-Ching Ho
Also filed as: HO BANG-CHING
10 granted patents·3 pending applications·94 citations·filing 2003–2012
87Inventor score
Top patents by PatentIndex Score
13 records- 0193US6982135B2Pattern compensation for stitchingTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Jan 3, 2006·54 cites·18 claims
- 0273US7452822B2Via plug formation in dual damascene processTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Nov 18, 2008·6 cites·23 claims
- 0369US7948096B2Semiconductor using specific contact angle for immersion lithographyTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted May 24, 2011·2 cites·16 claims
- 0469US7196005B2Dual damascene process with dummy featuresTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Mar 27, 2007·17 cites·20 claims
- 0568US9337052B2Silicon-containing EUV resist underlayer film forming compositionNISSAN CHEMICAL IND LTD·Filed 2012·Granted May 10, 2016·2 cites·13 claims
- 0661US7119035B2Method using specific contact angle for immersion lithographyTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Oct 10, 2006·5 cites·11 claims
- 0756US7611825B2Photolithography method to prevent photoresist pattern collapseTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Nov 3, 2009·4 cites·26 claims
- 0853US7135259B2Scatterometric method of monitoring hot plate temperature and facilitating critical dimension controlTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Nov 14, 2006·4 cites·20 claims
- 0947US7751025B2Scatterometric method of monitoring hot plate temperature and facilitating critical dimension controlTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Jul 6, 2010·0 cites·19 claims
- 1040US2006228894A1Method for semiconductor manufacturing using a negative photoresist with thermal flow propertiesTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 1139US7279793B2System and method for manufacturing semiconductor devices using an anti-reflective coating layerTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Oct 9, 2007·0 cites·13 claims
- 1239US2006223309A1Dual-damascene process for manufacturing semiconductor devicesTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 1337US2005170638A1Method for forming dual damascene interconnect structureFiled 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →