Inventor · disambiguated record
Herve Jaouen
Also filed as: JAOUEN HERVE
19 granted patents·1 pending application·442 citations·filing 1998–2018
94Inventor score
Files withST MICROELECTRONICS SA20
Top patents by PatentIndex Score
20 records- 0198US6031445ATransformer for integrated circuitsST MICROELECTRONICS SA·Filed 1998·Granted Feb 29, 2000·317 cites·18 claims
- 0283US9929039B2Method for manufacture of a semiconductor wafer suitable for the manufacture of an SOI substrate, and SOI substrate wafer thus obtainedST MICROELECTRONICS SA·Filed 2015·Granted Mar 27, 2018·3 cites·18 claims
- 0378US6670686B2Integrated sound transmitter and receiver, and corresponding method for making sameST MICROELECTRONICS SA·Filed 2000·Granted Dec 30, 2003·17 cites·34 claims
- 0475US7396736B2Magnetic sensor of very high sensitivityST MICROELECTRONICS SA·Filed 2005·Granted Jul 8, 2008·6 cites·10 claims
- 0570US6673703B2Method of fabricating an integrated circuitST MICROELECTRONICS SA·Filed 2002·Granted Jan 6, 2004·16 cites·20 claims
- 0666US6081030ASemiconductor device having separated exchange meansST MICROELECTRONICS SA·Filed 1998·Granted Jun 27, 2000·33 cites·19 claims
- 0761US6897545B2Lateral operation bipolar transistor and a corresponding fabrication processST MICROELECTRONICS SA·Filed 2002·Granted May 24, 2005·10 cites·12 claims
- 0858US6100595ASemiconductor device having optoelectronic remote signal-exchange meansST MICROELECTRONICS SA·Filed 1998·Granted Aug 8, 2000·24 cites·18 claims
- 0957US10535552B2Method for manufacture of a semiconductor wafer suitable for the manufacture of an SOI substrate, and SOI substrate wafer thus obtainedST MICROELECTRONICS SA·Filed 2018·Granted Jan 14, 2020·0 cites·18 claims
- 1056US6623993B2Method of determining the time for polishing the surface of an integrated circuit waferST MICROELECTRONICS SA·Filed 2001·Granted Sep 23, 2003·6 cites·13 claims
- 1150US7038285B2Very high sensitivity magnetic sensorST MICROELECTRONICS SA·Filed 2000·Granted May 2, 2006·3 cites·18 claims
- 1248US6756279B2Method for manufacturing a bipolar transistor in a CMOS integrated circuitST MICROELECTRONICS SA·Filed 2002·Granted Jun 29, 2004·3 cites·20 claims
- 1346US6503812B2Fabrication process for a semiconductor device with an isolated zoneST MICROELECTRONICS SA·Filed 2002·Granted Jan 7, 2003·2 cites·13 claims
- 1438US7029927B2Method of repairing an integrated electronic circuit using a formed electrical isolationST MICROELECTRONICS SA·Filed 2004·Granted Apr 18, 2006·0 cites·13 claims
- 1537US6423996B1Process for fabricating a metal-metal capacitor within an integrated circuit, and corresponding integrated circuitST MICROELECTRONICS SA·Filed 2000·Granted Jul 23, 2002·0 cites·15 claims
- 1635US6593204B2Method of fabricating a silicon-on-insulator system with thin semiconductor islets surrounded by an insulative materialST MICROELECTRONICS SA·Filed 2001·Granted Jul 15, 2003·0 cites·34 claims
- 1734US7029991B2Method for making a SOI semiconductor substrate with thin active semiconductor layerST MICROELECTRONICS SA·Filed 2001·Granted Apr 18, 2006·0 cites·20 claims
- 1834US6800514B2Method of fabricating a MOS transistor with a drain extension and corresponding transistorST MICROELECTRONICS SA·Filed 2002·Granted Oct 5, 2004·0 cites·18 claims
- 1933US2006258066A1Electrically stabilized integrated circuitST MICROELECTRONICS SA·Filed 2006·Application pending·0 cites
- 2032US6208551B1Memory circuit architectureST MICROELECTRONICS SA·Filed 1999·Granted Mar 27, 2001·2 cites·4 claims
Join the waitlist — get patent alerts
Get an alert when Herve Jaouen files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →