Inventor · disambiguated record
Hideyuki Iino
Also filed as: IINO HIDEYUKI
16 granted patents·343 citations·filing 1988–2000
95Inventor score
Files withFUJITSU LTD16
Top patents by PatentIndex Score
16 records- 0178US6877112B1Reset control system and methodFUJITSU LTD·Filed 2000·Granted Apr 5, 2005·29 cites·15 claims
- 0266US5809552AData processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditionsFUJITSU LTD·Filed 1996·Granted Sep 15, 1998·53 cites·13 claims
- 0365US4929854AClock circuit having a clocked output bufferFUJITSU LTD·Filed 1989·Granted May 29, 1990·36 cites·14 claims
- 0462US5768559AMultiple bank structured memory access device having flexible setting of a pipeline stage numberFUJITSU LTD·Filed 1996·Granted Jun 16, 1998·41 cites·8 claims
- 0561US4904883ASemiconductor integrated circuit having a DC test functionFUJITSU LTD·Filed 1988·Granted Feb 27, 1990·19 cites·3 claims
- 0651US5644748AProcessor system including an index buffer circuit and a translation look-aside buffer control circuit for processor-to-processor interfacingFUJITSU LTD·Filed 1993·Granted Jul 1, 1997·27 cites·11 claims
- 0750US5822557APipelined data processing device having improved hardware control over an arithmetic operations unitFUJITSU LTD·Filed 1996·Granted Oct 13, 1998·26 cites·20 claims
- 0850US5056011ADirect memory access controller with expedited error controlFUJITSU LTD·Filed 1989·Granted Oct 8, 1991·19 cites·17 claims
- 0945US5551010AArithmetic operation unit and memory accessing device for accessing primary and secondary cache memories independently of a CPUFUJITSU LTD·Filed 1992·Granted Aug 27, 1996·16 cites·9 claims
- 1044US5742842AData processing apparatus for executing a vector operation under control of a master processorFUJITSU LTD·Filed 1996·Granted Apr 21, 1998·19 cites·11 claims
- 1144US5586282AMemory system employing pipeline process for accessing memory banksFUJITSU LTD·Filed 1994·Granted Dec 17, 1996·15 cites·16 claims
- 1242US5654972AProcessor having test circuitFUJITSU LTD·Filed 1994·Granted Aug 5, 1997·13 cites·10 claims
- 1338US5724548ASystem including processor and cache memory and method of controlling the cache memoryFUJITSU LTD·Filed 1995·Granted Mar 3, 1998·10 cites·16 claims
- 1436US5699553AMemory accessing device for a pipeline information processing systemFUJITSU LTD·Filed 1992·Granted Dec 16, 1997·9 cites·14 claims
- 1533US5526494ABus controllerFUJITSU LTD·Filed 1991·Granted Jun 11, 1996·5 cites·13 claims
- 1632US5742839ACoprocessor for performing an arithmetic operation by automatically reading data from an external memoryFUJITSU LTD·Filed 1993·Granted Apr 21, 1998·6 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →