Inventor · disambiguated record
Samit Sengupta
Also filed as: SENGUPTA SAMIT · SENGUPTA SAMIT S
22 granted patents·8 pending applications·395 citations·filing 1997–2019
96Inventor score
Files withQUALCOMM INC11VLSI TECHNOLOGY INC5PHILIPS ELECTRONICS NA4ALTERA CORP3KONINKL PHILIPS ELECTRONICS NV3
Top patents by PatentIndex Score
30 records- 0189US6933869B1Integrated circuits with temperature-change and threshold-voltage drift compensationALTERA CORP·Filed 2004·Granted Aug 23, 2005·53 cites·20 claims
- 0286US7468617B1Electrostatic discharge (ESD) protection device for use with multiple I/O standardsALTERA CORP·Filed 2006·Granted Dec 23, 2008·12 cites·7 claims
- 0385US5915203AMethod for producing deep submicron interconnect viasVLSI TECHNOLOGY INC·Filed 1997·Granted Jun 22, 1999·80 cites·11 claims
- 0484US10490558B2Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cellsQUALCOMM INC·Filed 2017·Granted Nov 26, 2019·4 cites·14 claims
- 0582US10853542B1Fuse-based logic repairQUALCOMM INC·Filed 2019·Granted Dec 1, 2020·4 cites·20 claims
- 0680US6410421B1Semiconductor device with anti-reflective structure and methods of manufactureKONINKL PHILIPS ELECTRONICS NV·Filed 2000·Granted Jun 25, 2002·21 cites·20 claims
- 0779US7286020B1Techniques for monitoring and replacing circuits to maintain high performanceALTERA CORP·Filed 2005·Granted Oct 23, 2007·10 cites·20 claims
- 0877US6433433B1Semiconductor device with misaligned via holeKONINKL PHILIPS ELECTRONICS NV·Filed 2000·Granted Aug 13, 2002·22 cites·12 claims
- 0977US6207565B1Integrated process for ashing resist and treating silicon after masked spacer etchVLSI TECHNOLOGY INC·Filed 2000·Granted Mar 27, 2001·22 cites·14 claims
- 1074US6057587ASemiconductor device with anti-reflective structureVLSI TECHNOLOGY INC·Filed 1997·Granted May 2, 2000·37 cites·24 claims
- 1167US8217457B1Electrostatic discharge (ESD) protection device for use with multiple I/O standardsSENGUPTA SAMIT·Filed 2008·Granted Jul 10, 2012·4 cites·19 claims
- 1266US6176983B1Methods of forming a semiconductor deviceVLSI TECHNOLOGY INC·Filed 1997·Granted Jan 23, 2001·32 cites·24 claims
- 1364US6255226B1Optimized metal etch process to enable the use of aluminum plugsPHILIPS SEMICONDUCTOR INC·Filed 1998·Granted Jul 3, 2001·26 cites·24 claims
- 1464US6235609B1Method for forming isolation areas with improved isolation oxidePHILIPS ELECTRONICS NA·Filed 2000·Granted May 22, 2001·12 cites·22 claims
- 1556US6146996ASemiconductor device with conductive via and method of making samePHILIPS ELECTRONICS NA·Filed 1998·Granted Nov 14, 2000·18 cites·18 claims
- 1655US9076775B2System and method of varying gate lengths of multiple coresQUALCOMM INC·Filed 2013·Granted Jul 7, 2015·0 cites·37 claims
- 1752US9461040B2System and method of varying gate lengths of multiple coresQUALCOMM INC·Filed 2015·Granted Oct 4, 2016·0 cites·30 claims
- 1848US9245971B2Semiconductor device having high mobility channelQUALCOMM INC·Filed 2013·Granted Jan 26, 2016·0 cites·45 claims
- 1945US2016093511A1Multigate transistor device and method of isolating adjacent transistors in multigate transistor device using self-aligned diffusion break (sadb)QUALCOMM INC·Filed 2014·Application pending·0 cites
- 2044US6162586AMethod for substantially preventing footings in chemically amplified deep ultra violet photoresist layersPHILIPS ELECTRONICS NA·Filed 1998·Granted Dec 19, 2000·11 cites·19 claims
- 2142US6413152B1Apparatus for performing chemical-mechanical planarization with improved process window, process flexibility and costPHILIPS ELECTRONICS NA·Filed 1999·Granted Jul 2, 2002·9 cites·19 claims
- 2242US6228757B1Process for forming metal interconnects with reduced or eliminated metal recess in viasPHILIPS SEMICONDUCTORS INC·Filed 1998·Granted May 8, 2001·9 cites·23 claims
- 2342US2020251473A1High density fin field-effect transistor (finfet)QUALCOMM INC·Filed 2019·Application pending·0 cites
- 2441US6459153B1Compositions for improving interconnect metallization performance in integrated circuitsKONINKL PHILIPS ELECTRONICS NV·Filed 1999·Granted Oct 1, 2002·9 cites·15 claims
- 2541US2015001631A1Cmos technology integrationQUALCOMM INC·Filed 2013·Application pending·0 cites
- 2638US2020027801A1Test structure for inline detection of interlayer metal defectsQUALCOMM INC·Filed 2019·Application pending·0 cites
- 2738US2001017416A1Device having metal interconnects with reduced or eliminated metal recess in viasVLSI TECHNOLOGY INC·Filed 2001·Application pending·0 cites
- 2838US2001012690A1Optimized metal etch process to enable the use of aluminum plugsPHILIPS SEMICONDUCTORS INC·Filed 2001·Application pending·0 cites
- 2937US2020098920A1Transistor gate structureQUALCOMM INC·Filed 2018·Application pending·0 cites
- 3037US2020166566A1Intralayer conductive defect detection structureQUALCOMM INC·Filed 2018·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →