Inventor · disambiguated record
Rajendran Panda
Also filed as: PANDA RAJENDRAN · PANDA RAJENDRAN V
10 granted patents·156 citations·filing 1997–2015
90Inventor score
Technology areasG06F
Top patents by PatentIndex Score
10 records- 0187US7698677B2On-chip decoupling capacitance and power/ground network wire co-optimization to reduce dynamic noiseFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Apr 13, 2010·20 cites·13 claims
- 0283US7571404B2Fast on-chip decoupling capacitance budgeting method and device for reduced power supply noiseFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Aug 4, 2009·15 cites·20 claims
- 0376US6819538B2Method and apparatus for controlling current demand in an integrated circuitFREESCALE SEMICONDUCTOR INC·Filed 2001·Granted Nov 16, 2004·24 cites·19 claims
- 0473US7149674B1Methods for analyzing integrated circuits and apparatus thereforFREESCALE SEMICONDUCTOR INC·Filed 2000·Granted Dec 12, 2006·22 cites·43 claims
- 0572US7127384B2Fast simulation of circuitry having SOI transistorsFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Oct 24, 2006·30 cites·18 claims
- 0669US7251797B2Pessimism reduction in crosstalk noise aware static timing analysisFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jul 31, 2007·18 cites·22 claims
- 0766US9176732B2Method and apparatus for minimum cost cycle removal from a directed graphORACLE INT CORP·Filed 2013·Granted Nov 3, 2015·3 cites·19 claims
- 0861US7093223B2Noise analysis for an integrated circuit modelFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Aug 15, 2006·9 cites·27 claims
- 0955US9507903B2Method for estimation of delays and slews during circuit optimizationORACLE INT CORP·Filed 2015·Granted Nov 29, 2016·1 cites·20 claims
- 1038US6074429AOptimizing combinational circuit layout through iterative restructuringMOTOROLA INC·Filed 1997·Granted Jun 13, 2000·14 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →