Inventor · disambiguated record
Sanjay S. Talreja
Also filed as: TALREJA SANJAY · TALREJA SANJAY S
25 granted patents·1 pending application·1,860 citations·filing 1992–2006
98Inventor score
Top patents by PatentIndex Score
26 records- 0198US5539690AWrite verify schemes for flash memory with multilevel cellsINTEL CORP·Filed 1994·Granted Jul 23, 1996·314 cites·24 claims
- 0297US5485422ADrain bias multiplexing for multiple bit flash cellINTEL CORP·Filed 1994·Granted Jan 16, 1996·223 cites·43 claims
- 0395US5317535AGate/source disturb protection for sixteen-bit flash EEPROM memory arraysINTEL CORP·Filed 1992·Granted May 31, 1994·132 cites·9 claims
- 0493US6097637ADynamic single bit per cell to multiple bit per cell memoryINTEL CORP·Filed 1996·Granted Aug 1, 2000·109 cites·12 claims
- 0592US6154819AApparatus and method using volatile lock and lock-down registers and for protecting memory blocksINTEL CORP·Filed 1998·Granted Nov 28, 2000·112 cites·11 claims
- 0692US5280447AFloating gate nonvolatile memory with configurable erasure blocksINTEL CORP·Filed 1992·Granted Jan 18, 1994·105 cites·20 claims
- 0791US5742787AHardware reset of a write state machine for flash memoryINTEL CORP·Filed 1995·Granted Apr 21, 1998·89 cites·17 claims
- 0890US6223290B1Method and apparatus for preventing the fraudulent use of a cellular telephoneINTEL CORP·Filed 1998·Granted Apr 24, 2001·166 cites·49 claims
- 0989US6088264AFlash memory partitioning for read-while-write operationINTEL CORP·Filed 1998·Granted Jul 11, 2000·77 cites·23 claims
- 1089US5828616ASensing scheme for flash memory with multilevel cellsINTEL CORP·Filed 1997·Granted Oct 27, 1998·71 cites·2 claims
- 1188US5944837AControlling flash memory program and erase pulsesINTEL CORP·Filed 1997·Granted Aug 31, 1999·62 cites·40 claims
- 1288US5438546AProgrammable redundancy scheme suitable for single-bit state and multibit state nonvolatile memoriesINTEL CORP·Filed 1994·Granted Aug 1, 1995·78 cites·15 claims
- 1387US5748546ASensing scheme for flash memory with multilevel cellsINTEL CORP·Filed 1997·Granted May 5, 1998·62 cites·3 claims
- 1478US6931498B2Status register architecture for flexible read-while-write deviceINTEL CORP·Filed 2001·Granted Aug 16, 2005·28 cites·12 claims
- 1577US5907700AControlling flash memory program and erase pulsesINTEL CORP·Filed 1997·Granted May 25, 1999·36 cites·17 claims
- 1675US5933026ASelf-configuring interface architecture on flash memoriesINTEL CORP·Filed 1997·Granted Aug 3, 1999·39 cites·26 claims
- 1775US5267196AFloating gate nonvolatile memory with distributed blocking featureINTEL CORP·Filed 1992·Granted Nov 30, 1993·37 cites·19 claims
- 1871US5684741AAuto-verification of programming flash memory cellsINTEL CORP·Filed 1995·Granted Nov 4, 1997·31 cites·17 claims
- 1970US6587373B2Multilevel cell memory architectureINTEL CORP·Filed 2002·Granted Jul 1, 2003·14 cites·4 claims
- 2067US5896338AInput/output power supply detection scheme for flash memoryINTEL CORP·Filed 1997·Granted Apr 20, 1999·26 cites·28 claims
- 2164US6920539B2Method and system to retrieve informationINTEL CORP·Filed 2002·Granted Jul 19, 2005·10 cites·10 claims
- 2264US6618790B1Burst suspend and resume with computer memoryINTEL CORP·Filed 2000·Granted Sep 9, 2003·13 cites·14 claims
- 2363US6483743B1Multilevel cell memory architectureINTEL CORP·Filed 2001·Granted Nov 19, 2002·10 cites·17 claims
- 2455US8489780B2Power saving in NAND flash memorySUNDARAM RAJESH·Filed 2006·Granted Jul 16, 2013·3 cites·14 claims
- 2549US5379413AUser selectable word/byte input architecture for flash EEPROM memory write and erase operationsINTEL CORP·Filed 1992·Granted Jan 3, 1995·13 cites·29 claims
- 2646US2006143371A1Integrated memory management apparatus, systems, and methodsRUDELIC JOHN C·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →