Inventor · disambiguated record
Been-Jon Woo
Also filed as: WOO BEEN J · WOO BEEN-JON · WOO BEEN-JON K
17 granted patents·8 pending applications·701 citations·filing 1986–2007
96Inventor score
Top patents by PatentIndex Score
25 records- 0192US4728617AMethod of fabricating a MOSFET with graded source and drain regionsINTEL CORP·Filed 1986·Granted Mar 1, 1988·121 cites·5 claims
- 0291US5210047AProcess for fabricating a flash EPROM having reduced cell sizeWOO BEEN JON K·Filed 1991·Granted May 11, 1993·130 cites·16 claims
- 0387US7348618B2Flash memory cell having reduced floating gate to floating gate couplingINTEL CORP·Filed 2005·Granted Mar 25, 2008·10 cites·16 claims
- 0486US7465625B2Flash memory cell having reduced floating gate to floating gate couplingWOO BEEN-JON K·Filed 2006·Granted Dec 16, 2008·10 cites·10 claims
- 0584US4757026ASource drain doping techniqueINTEL CORP·Filed 1987·Granted Jul 12, 1988·54 cites·2 claims
- 0682US5075245AMethod for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal stepsINTEL CORP·Filed 1991·Granted Dec 24, 1991·81 cites·9 claims
- 0781US5229631AErase performance improvement via dual floating gate processingINTEL CORP·Filed 1992·Granted Jul 20, 1993·50 cites·16 claims
- 0878US5147813AErase performance improvement via dual floating gate processingINTEL CORP·Filed 1991·Granted Sep 15, 1992·43 cites·23 claims
- 0974US5470772ASilicidation method for contactless EPROM related devicesINTEL CORP·Filed 1993·Granted Nov 28, 1995·32 cites·24 claims
- 1073US4784965ASource drain doping techniqueINTEL CORP·Filed 1987·Granted Nov 15, 1988·33 cites·5 claims
- 1167US5102814AMethod for improving device scalability of buried bit line flash EPROM devices having short reoxidation beaks and shallower junctionsINTEL CORP·Filed 1990·Granted Apr 7, 1992·43 cites·25 claims
- 1263US7632736B2Self-aligned contact formation utilizing sacrificial polysiliconINTEL CORP·Filed 2007·Granted Dec 15, 2009·3 cites·12 claims
- 1362US4833099ATungsten-silicide reoxidation process including annealing in pure nitrogen and subsequent oxidation in oxygenINTEL CORP·Filed 1988·Granted May 23, 1989·28 cites·12 claims
- 1454US7015149B2Simplified dual damascene processGRACE SEMICONDUCTOR MFG CORP·Filed 2004·Granted Mar 21, 2006·6 cites·12 claims
- 1554US5077230AMethod for improving erase characteristics of buried bit line flash EPROM devices by use of a thin nitride layer formed during field oxide growthINTEL CORP·Filed 1990·Granted Dec 31, 1991·25 cites·13 claims
- 1654US4774201ATungsten-silicide reoxidation technique using a CVD oxide capINTEL CORP·Filed 1988·Granted Sep 27, 1988·21 cites·5 claims
- 1746US5196361AMethod of making source junction breakdown for devices with source-side erasingINTEL CORP·Filed 1991·Granted Mar 23, 1993·11 cites·26 claims
- 1842US2007210030A1Method of patterning conductive structureWOO BEEN-JON·Filed 2006·Application pending·0 cites
- 1938US2009001440A1Semiconductor device with buried source railWEI MAX·Filed 2007·Application pending·0 cites
- 2036US2005059235A1Method for improving oxide layer flatnessFiled 2004·Application pending·0 cites
- 2136US2005048754A1Processing method for increasing packaging density of an integrated circuitFiled 2004·Application pending·0 cites
- 2236US2006134881A1Method of forming trench isolation device capable of reducing corner recessWOO BEEN-JON·Filed 2004·Application pending·0 cites
- 2336US2005090084A1Method of forming a gate structureFiled 2004·Application pending·0 cites
- 2434US2005085060A1Self-aligned silicide process for preventing electrical shortsFiled 2004·Application pending·0 cites
- 2530US2007281403A1Method of enhancing gate lithography performance by polysilicon chemical-mechanical polishingTSAI MON-CHIN·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →