Inventor · disambiguated record
Rahul Sahu
Also filed as: SAHU RAHUL
32 granted patents·11 pending applications·169 citations·filing 2012–2024
96Inventor score
Top patents by PatentIndex Score
43 records- 0197US11049552B1Write assist circuitry for memoryQUALCOMM INC·Filed 2020·Granted Jun 29, 2021·7 cites·20 claims
- 0296US9455028B1Adaptive negative bit line write assistQUALCOMM INC·Filed 2015·Granted Sep 27, 2016·29 cites·20 claims
- 0395US11955169B2High-speed multi-port memory supporting collisionQUALCOMM INC·Filed 2021·Granted Apr 9, 2024·4 cites·9 claims
- 0495US9865337B1Write data path to reduce charge leakage of negative boostQUALCOMM INC·Filed 2017·Granted Jan 9, 2018·20 cites·20 claims
- 0592US8830766B2Margin free PVT tolerant fast self-timed sense amplifier reset circuitLSI CORP·Filed 2013·Granted Sep 9, 2014·16 cites·20 claims
- 0691US9177633B2Bit line write assist for static random access memory architecturesLSI CORP·Filed 2014·Granted Nov 3, 2015·16 cites·19 claims
- 0790US9916892B1Write driver circuitry to reduce leakage of negative boost chargeQUALCOMM INC·Filed 2017·Granted Mar 13, 2018·10 cites·17 claims
- 0888US11152921B1Systems and methods for control signal latching in memoriesQUALCOMM INC·Filed 2021·Granted Oct 19, 2021·2 cites·28 claims
- 0988US8923090B1Address decoding circuits for reducing address and memory enable setup timeLSI CORP·Filed 2013·Granted Dec 30, 2014·12 cites·21 claims
- 1082US11935606B2Memory with scan chain testing of column redundancy logic and multiplexingQUALCOMM INC·Filed 2021·Granted Mar 19, 2024·1 cites·17 claims
- 1182US9111637B1Differential latch word line assist for SRAMLSI CORP·Filed 2014·Granted Aug 18, 2015·8 cites·20 claims
- 1281US10811088B2Access assist with wordline adjustment with tracking cellQUALCOMM INC·Filed 2019·Granted Oct 20, 2020·5 cites·13 claims
- 1381US9928898B2Wordline adjustment schemeQUALCOMM INC·Filed 2016·Granted Mar 27, 2018·5 cites·29 claims
- 1481US9721650B1Architecture to improve write-ability in SRAMQUALCOMM INC·Filed 2016·Granted Aug 1, 2017·6 cites·16 claims
- 1580US12020766B2Memory circuit architecture with multiplexing between memory banksQUALCOMM INC·Filed 2022·Granted Jun 25, 2024·1 cites·15 claims
- 1680US8811070B1Write-tracking circuitry for memory devicesLSI CORP·Filed 2013·Granted Aug 19, 2014·7 cites·17 claims
- 1774US12327599B2Memory with scan chain testing of column redundancy logic and multiplexingQUALCOMM INC·Filed 2024·Granted Jun 10, 2025·0 cites·14 claims
- 1874US10614865B1Boost generation circuitry for memoryQUALCOMM INC·Filed 2018·Granted Apr 7, 2020·3 cites·19 claims
- 1972US12183393B2High-speed multi-port memory supporting collisionQUALCOMM INC·Filed 2024·Granted Dec 31, 2024·0 cites·9 claims
- 2071US9281055B2Memory sense amplifier and column pre-chargerLSI CORP·Filed 2014·Granted Mar 8, 2016·4 cites·20 claims
- 2171US9177635B1Dual rail single-ended read data paths for static random access memoriesLSI CORP·Filed 2014·Granted Nov 3, 2015·4 cites·11 claims
- 2265US10811086B1SRAM write yield enhancement with pull-up strength modulationQUALCOMM INC·Filed 2019·Granted Oct 20, 2020·2 cites·20 claims
- 2365US2024312496A1Memory circuit architecture with multiplexing between memory banksQUALCOMM INC·Filed 2024·Application pending·0 cites
- 2459US10867668B2Area efficient write data path circuit for SRAM yield enhancementQUALCOMM INC·Filed 2017·Granted Dec 15, 2020·1 cites·32 claims
- 2557US2025335117A1Write data path for high-speed time-shared serial read write memories having write maskQUALCOMM INC·Filed 2024·Application pending·0 cites
- 2653US12047073B2Power supply circuit with reduced leakage currentQUALCOMM INC·Filed 2021·Granted Jul 23, 2024·0 cites·25 claims
- 2753US11837313B2Memory with efficient DVS controlled by asynchronous inputsQUALCOMM INC·Filed 2021·Granted Dec 5, 2023·0 cites·23 claims
- 2851US11972834B2Low power and robust level-shifting pulse latch for dual-power memoriesQUALCOMM INC·Filed 2020·Granted Apr 30, 2024·0 cites·25 claims
- 2951US8879303B2Pre-charge tracking of global read lines in high speed SRAMLSI CORP·Filed 2013·Granted Nov 4, 2014·2 cites·22 claims
- 3051US2025218506A1Time multiplexing of cleanup and write for serial read write memoryQUALCOMM INC·Filed 2024·Application pending·0 cites
- 3148US2024321376A1Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier OffsetQUALCOMM INC·Filed 2023·Application pending·0 cites
- 3245US12020746B2Memory write assist with reduced switching powerQUALCOMM INC·Filed 2022·Granted Jun 25, 2024·0 cites·18 claims
- 3345US8923069B2Memory having self-timed edge-detection write trackingSAHU RAHUL·Filed 2012·Granted Dec 30, 2014·2 cites·22 claims
- 3445US8792267B1Memory having sense amplifier for output tracking by controlled feedback latchLSI COPORATION·Filed 2013·Granted Jul 29, 2014·2 cites·16 claims
- 3544US2025246232A1Hybrid boosting for memory write assistQUALCOMM INC·Filed 2024·Application pending·0 cites
- 3641US10839866B1Memory core power-up with reduced peak currentQUALCOMM INC·Filed 2019·Granted Nov 17, 2020·0 cites·12 claims
- 3737US2015138864A1Memory architecture with alternating segments and multiple bitlinesLSI CORP·Filed 2013·Application pending·0 cites
- 3837US2015302918A1Word line decoders for dual rail static random access memoriesLSI CORP·Filed 2014·Application pending·0 cites
- 3937US2015138863A1Interleaved write assist for hierarchical bitline sram architecturesLSI CORP·Filed 2013·Application pending·0 cites
- 4036US2015213881A1Integrated read/write tracking in sramLSI CORP·Filed 2014·Application pending·0 cites
- 4136US2015085592A1Bit-Line Discharge Assistance in Memory DevicesLSI CORP·Filed 2013·Application pending·0 cites
- 4224US9047936B2Memory device having control circuitry for write tracking using feedback-based controllerVikash·Filed 2012·Granted Jun 2, 2015·0 cites·20 claims
- 4321US2014071783A1Memory device with clock generation based on segmented address change detectionSAHU RAHUL·Filed 2012·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Rahul Sahu files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →