Inventor · disambiguated record
Gregory W. Alexander
Also filed as: ALEXANDER GREGORY W · ALEXANDER GREGORY WILLIAM
73 granted patents·7 pending applications·253 citations·filing 2003–2024
98Inventor score
Top patents by PatentIndex Score
80 records- 0193US11487672B1Multiple copy scoping bits for cache memoryIBM·Filed 2021·Granted Nov 1, 2022·7 cites·25 claims
- 0293US8521992B2Predicting and avoiding operand-store-compare hazards in out-of-order microprocessorsALEXANDER GREGORY W·Filed 2010·Granted Aug 27, 2013·21 cites·24 claims
- 0391US9542233B1Managing a free list of resources to decrease control complexity and reduce power consumptionIBM·Filed 2016·Granted Jan 10, 2017·6 cites·1 claims
- 0490US7254678B2Enhanced STCX design to improve subsequent load efficiencyIBM·Filed 2005·Granted Aug 7, 2007·38 cites·20 claims
- 0589US8015362B2Method and system for handling cache coherency for self-modifying codeIBM·Filed 2008·Granted Sep 6, 2011·21 cites·10 claims
- 0685US11853212B2Preemptive tracking of remote requests for decentralized hot cache line fairness trackingIBM·Filed 2022·Granted Dec 26, 2023·1 cites·20 claims
- 0784US12038841B2Decentralized hot cache line tracking fairness mechanismIBM·Filed 2022·Granted Jul 16, 2024·1 cites·25 claims
- 0881US10929142B2Making precise operand-store-compare predictions to avoid false dependenciesIBM·Filed 2019·Granted Feb 23, 2021·3 cites·19 claims
- 0981US8661230B2Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executionsALEXANDER GREGORY W·Filed 2011·Granted Feb 25, 2014·5 cites·7 claims
- 1080US8667258B2High performance cache translation look-aside buffer (TLB) lookups using multiple page size predictionPRASKY BRIAN R·Filed 2010·Granted Mar 4, 2014·6 cites·20 claims
- 1180US7032097B2Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cacheIBM·Filed 2003·Granted Apr 18, 2006·28 cites·24 claims
- 1279US10353817B2Cache miss thread balancingIBM·Filed 2017·Granted Jul 16, 2019·2 cites·23 claims
- 1379US9430235B2Predicting and avoiding operand-store-compare hazards in out-of-order microprocessorsIBM·Filed 2013·Granted Aug 30, 2016·4 cites·20 claims
- 1479US9069546B2Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executionsALEXANDER GREGORY W·Filed 2012·Granted Jun 30, 2015·4 cites·7 claims
- 1579US8468325B2Predicting and avoiding operand-store-compare hazards in out-of-order microprocessorsALEXANDER GREGORY W·Filed 2009·Granted Jun 18, 2013·9 cites·19 claims
- 1679US7769984B2Dual-issuance of microprocessor instructions using dual dependency matricesIBM·Filed 2008·Granted Aug 3, 2010·9 cites·1 claims
- 1778US10007526B2Freelist based global completion table having both thread-specific and global completion table identifiersIBM·Filed 2015·Granted Jun 26, 2018·2 cites·11 claims
- 1876US7306871B2Hybrid power generating system combining a fuel cell and a gas turbineDELPHI TECH INC·Filed 2004·Granted Dec 11, 2007·16 cites·18 claims
- 1976US7120784B2Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environmentIBM·Filed 2003·Granted Oct 10, 2006·23 cites·28 claims
- 2075US8433855B2Serializing translation lookaside buffer access around address translation parameter modificationALEXANDER GREGORY W·Filed 2008·Granted Apr 30, 2013·7 cites·18 claims
- 2174US7674538B2Apparatus and method for high efficiency operation of a high temperature fuel cell systemDELPHI TECH INC·Filed 2004·Granted Mar 9, 2010·14 cites·11 claims
- 2271US10956168B2Post completion execution in an out-of-order processor designIBM·Filed 2019·Granted Mar 23, 2021·1 cites·16 claims
- 2371US8453124B2Collecting computer processor instrumentation dataALEXANDER GREGORY W·Filed 2009·Granted May 28, 2013·5 cites·20 claims
- 2470US10592422B2Data-less history buffer with banked restore ports in a register mapperIBM·Filed 2017·Granted Mar 17, 2020·1 cites·19 claims
- 2569US7549095B1Error detection enhancement in a microprocessor through the use of a second dependency matrixIBM·Filed 2008·Granted Jun 16, 2009·4 cites·1 claims
- 2668US11068303B2Adjusting thread balancing in response to disruptive complex instructionIBM·Filed 2019·Granted Jul 20, 2021·1 cites·10 claims
- 2766US10102002B2Dynamic issue masks for processor hang preventionIBM·Filed 2014·Granted Oct 16, 2018·1 cites·7 claims
- 2866US10007525B2Freelist based global completion table having both thread-specific and global completion table identifiersIBM·Filed 2014·Granted Jun 26, 2018·1 cites·20 claims
- 2964US11360775B2Slice-based allocation history bufferIBM·Filed 2020·Granted Jun 14, 2022·0 cites·20 claims
- 3064US7039768B2Cache predictor for simultaneous multi-threaded processor system supporting multiple transactionsIBM·Filed 2003·Granted May 2, 2006·10 cites·36 claims
- 3163US12423234B1Cache governance in a computing environment with multiple processorsIBM·Filed 2024·Granted Sep 23, 2025·0 cites·20 claims
- 3262US12493553B2Cross-core invalidation snapshot managementIBM·Filed 2022·Granted Dec 9, 2025·0 cites·20 claims
- 3362US11907125B2Hot line fairness mechanism favoring software forward progressIBM·Filed 2022·Granted Feb 20, 2024·0 cites·20 claims
- 3462US10884754B2Infinite processor thread balancingIBM·Filed 2019·Granted Jan 5, 2021·0 cites·20 claims
- 3561US12099845B2Load reissuing using an alternate issue queueIBM·Filed 2022·Granted Sep 24, 2024·0 cites·17 claims
- 3661US11182168B2Post completion execution in an out-of-order processor designIBM·Filed 2020·Granted Nov 23, 2021·0 cites·20 claims
- 3761US10963380B2Cache miss thread balancingIBM·Filed 2019·Granted Mar 30, 2021·0 cites·18 claims
- 3860US11989128B1Invalidity protection for shared cache linesIBM·Filed 2022·Granted May 21, 2024·0 cites·20 claims
- 3960US11782777B1Preventing extraneous messages when exiting core recoveryIBM·Filed 2022·Granted Oct 10, 2023·0 cites·20 claims
- 4059US11977486B2Shadow pointer directory in an inclusive hierarchical cacheIBM·Filed 2022·Granted May 7, 2024·0 cites·20 claims
- 4159US11907132B2Final cache directory state indicationIBM·Filed 2022·Granted Feb 20, 2024·0 cites·22 claims
- 4259US11782836B1Multiprocessor system cache management with non-authority designationIBM·Filed 2022·Granted Oct 10, 2023·0 cites·20 claims
- 4359US11748266B1Special tracking pool enhancement for core local cache address invalidatesIBM·Filed 2022·Granted Sep 5, 2023·0 cites·20 claims
- 4458US10884752B2Slice-based allocation history bufferIBM·Filed 2017·Granted Jan 5, 2021·0 cites·20 claims
- 4557US9703614B2Managing a free list of resources to decrease control complexity and reduce power consumptionIBM·Filed 2016·Granted Jul 11, 2017·0 cites·1 claims
- 4656US9342307B2Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executionsIBM·Filed 2013·Granted May 17, 2016·0 cites·15 claims
- 4756US8082467B2Triggering workaround capabilities based on events active in a processor pipelineALEXANDER GREGORY W·Filed 2009·Granted Dec 20, 2011·1 cites·21 claims
- 4855US11880304B2Cache management using cache scope designationIBM·Filed 2022·Granted Jan 23, 2024·0 cites·20 claims
- 4955US11620231B2Lateral persistence directory statesIBM·Filed 2021·Granted Apr 4, 2023·0 cites·25 claims
- 5055US10558464B2Infinite processor thread balancingIBM·Filed 2017·Granted Feb 11, 2020·0 cites·17 claims
Showing the top 50 of 80 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Gregory W. Alexander files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →