Inventor · disambiguated record
Daniel Chu
Also filed as: CHU DANIEL · CHU DANIEL J
23 granted patents·1 pending application·62 citations·filing 2004–2022
93Inventor score
Top patents by PatentIndex Score
24 records- 0190US10032508B1Method and apparatus for multi-level setback read for three dimensional crosspoint memoryINTEL CORP·Filed 2016·Granted Jul 24, 2018·9 cites·20 claims
- 0290US9286975B2Mitigating read disturb in a cross-point memoryINTEL CORP·Filed 2014·Granted Mar 15, 2016·18 cites·12 claims
- 0389US11354040B2Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memoryMICRON TECHNOLOGY INC·Filed 2020·Granted Jun 7, 2022·2 cites·14 claims
- 0484US8913425B2Phase change memory maskINTEL CORP·Filed 2013·Granted Dec 16, 2014·6 cites·23 claims
- 0574US9406378B2Phase change memory with mask receiverINTEL CORP·Filed 2014·Granted Aug 2, 2016·3 cites·20 claims
- 0672US11768603B2Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memoryMICRON TECHNOLOGY INC·Filed 2022·Granted Sep 26, 2023·0 cites·20 claims
- 0772US9747977B2Methods and systems for verifying cell programming in phase change memoryCHU DANIEL J·Filed 2013·Granted Aug 29, 2017·4 cites·20 claims
- 0871US10037799B2Phase change memory with mask receiverINTEL CORP·Filed 2016·Granted Jul 31, 2018·2 cites·17 claims
- 0971US8630107B2Self-disabling chip enable inputCHU DANIEL J·Filed 2012·Granted Jan 14, 2014·3 cites·18 claims
- 1070US11243658B1Intelligent directives for user interface interactionsPINTEREST INC·Filed 2017·Granted Feb 8, 2022·3 cites·20 claims
- 1169US10719237B2Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memoryMICRON TECHNOLOGY INC·Filed 2016·Granted Jul 21, 2020·2 cites·24 claims
- 1267US9196316B2Self-disabling chip enable inputCHU DANIEL·Filed 2011·Granted Nov 24, 2015·2 cites·6 claims
- 1357US8860488B2Apparatuses and method for shifting a voltage levelMICRON TECHNOLOGY INC·Filed 2013·Granted Oct 14, 2014·1 cites·23 claims
- 1455US10553286B2Tailoring timing offsets during a programming pulse for a memory deviceINTEL CORP·Filed 2018·Granted Feb 4, 2020·1 cites·28 claims
- 1555US7317346B2Selecting a bias for a level shifting deviceINTEL CORP·Filed 2005·Granted Jan 8, 2008·3 cites·13 claims
- 1651US12041051B2Techniques for anonymous rate limiting for servicesAPPLE INC·Filed 2022·Granted Jul 16, 2024·0 cites·20 claims
- 1750US11024380B2Dual demarcation voltage sensing before writesINTEL CORP·Filed 2019·Granted Jun 1, 2021·0 cites·11 claims
- 1850US7570466B2Dual mode negative voltage switchingINTEL CORP·Filed 2005·Granted Aug 4, 2009·1 cites·29 claims
- 1949US10438659B2Method and apparatus for multi-level setback read for three dimensional crosspoint memoryINTEL CORP·Filed 2018·Granted Oct 8, 2019·0 cites·26 claims
- 2049US7382591B2Cascode protected negative voltage switchingINTEL CORP·Filed 2005·Granted Jun 3, 2008·2 cites·30 claims
- 2145US10325652B2Cell programming verificationINTEL CORP·Filed 2017·Granted Jun 18, 2019·0 cites·25 claims
- 2244US10482960B2Dual demarcation voltage sensing before writesINTEL CORP·Filed 2016·Granted Nov 19, 2019·0 cites·14 claims
- 2337US2021090652A1Techniques to generate & adjust program current pulses for cross-point nonvolatile memoryINTEL CORP·Filed 2019·Application pending·0 cites
- 2435US7116151B2Stress tolerant high voltage back-to-back switchINTEL CORP·Filed 2004·Granted Oct 3, 2006·0 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →