Inventor · disambiguated record
Gautam Doshi
Also filed as: DOSHI GAUTAM · DOSHI GAUTAM B · DOSHI GAUTAM BHAGWANDAS
25 granted patents·4 pending applications·750 citations·filing 1996–2018
97Inventor score
Top patents by PatentIndex Score
29 records- 0187US6820250B2Mechanism for software pipelining loop nestsINTEL CORP·Filed 2002·Granted Nov 16, 2004·49 cites·29 claims
- 0286US6151669AMethods and apparatus for efficient control of floating-point status registerINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Nov 21, 2000·122 cites·31 claims
- 0382US6292886B1Scalar hardware for performing SIMD operationsINTEL CORP·Filed 1998·Granted Sep 18, 2001·107 cites·19 claims
- 0481US11256489B2Nested loops reversal enhancementsINTEL CORPORTATION·Filed 2017·Granted Feb 22, 2022·4 cites·24 claims
- 0575US9552205B2Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructionsINTEL CORP·Filed 2013·Granted Jan 24, 2017·3 cites·25 claims
- 0675US7533300B2Configurable error handling apparatus and methods to operate the sameINTEL CORP·Filed 2006·Granted May 12, 2009·8 cites·23 claims
- 0774US6192515B1Method for software pipelining nested loopsINTEL CORP·Filed 1998·Granted Feb 20, 2001·76 cites·25 claims
- 0873US9465647B2Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAMINTEL CORP·Filed 2013·Granted Oct 11, 2016·2 cites·12 claims
- 0972US7035891B2Reduced-hardware soft error detectionINTEL CORP·Filed 2002·Granted Apr 25, 2006·17 cites·32 claims
- 1072US6301705B1System and method for deferring exceptions generated during speculative executionINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Oct 9, 2001·59 cites·17 claims
- 1171US8578138B2Enabling storage of active state in internal storage of processor rather than in SMRAM upon entry to system management modeNATU MAHESH S·Filed 2009·Granted Nov 5, 2013·4 cites·12 claims
- 1270US7263692B2System and method for software-pipelining of loops with sparse matrix routinesINTEL CORP·Filed 2003·Granted Aug 28, 2007·15 cites·25 claims
- 1370US6542966B1Method and apparatus for managing temporal and non-temporal data in a single cache structureINTEL CORP·Filed 1998·Granted Apr 1, 2003·54 cites·23 claims
- 1464US9450888B2Providing a bufferless transport method for multi-dimensional mesh topologyINTEL CORP·Filed 2013·Granted Sep 20, 2016·1 cites·14 claims
- 1561US8593960B2Providing a bufferless transport method for multi-dimensional mesh topologyKAUSCHKE MICHAEL·Filed 2010·Granted Nov 26, 2013·1 cites·14 claims
- 1661US6243734B1Computer product and method for sparse matricesINTEL CORP·Filed 1998·Granted Jun 5, 2001·39 cites·138 claims
- 1760US6321330B1Each iteration array selective loop data prefetch in multiple data width prefetch system using rotating register and parameterization to avoid redundant prefetchINTEL CORP·Filed 1999·Granted Nov 20, 2001·34 cites·35 claims
- 1859US6378067B1Exception reporting architecture for SIMD-FP instructionsIDEA CORP·Filed 1998·Granted Apr 23, 2002·35 cites·17 claims
- 1959US2018143923A1Providing State Storage in a Processor for System Management ModeINTEL CORP·Filed 2018·Application pending·0 cites
- 2057US6321327B1Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operationsINTEL CORP·Filed 1998·Granted Nov 20, 2001·32 cites·11 claims
- 2150US6370639B1Processor architecture having two or more floating-point status fieldsINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Apr 9, 2002·23 cites·43 claims
- 2249US5793654ASaturating alignment shifterINTEL CORP·Filed 1996·Granted Aug 11, 1998·22 cites·21 claims
- 2348US10169268B2Providing state storage in a processor for system management modeINTEL CORP·Filed 2016·Granted Jan 1, 2019·0 cites·20 claims
- 2448US6578059B1Methods and apparatus for controlling exponent range in floating-point calculationsINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Jun 10, 2003·20 cites·22 claims
- 2541US6212539B1Methods and apparatus for handling and storing bi-endian words in a floating-point processorINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Apr 3, 2001·13 cites·14 claims
- 2639US2002161812A1Computer product and method for sparse matricesFiled 2001·Application pending·0 cites
- 2739US2004123280A1Dependence compensation for sparse computationsFiled 2002·Application pending·0 cites
- 2836US6009263AEmulating agent and method for reformatting computer instructions into a standard uniform formatINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Dec 28, 1999·10 cites·14 claims
- 2936US2007106914A1Power management by adding special instructions during program translationMUTHUKUMAR KALYAN·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →