Inventor · disambiguated record
Mamun Ur Rashid
Also filed as: RASHID MAMUN · RASHID MAMUN U · RASHID MAMUN UR
23 granted patents·1 pending application·957 citations·filing 1993–2008
96Inventor score
Top patents by PatentIndex Score
24 records- 0197US5523972AMethod and apparatus for verifying the programming of multi-level flash EEPROM memoryINTEL CORP·Filed 1994·Granted Jun 4, 1996·277 cites·20 claims
- 0294US5822256AMethod and circuitry for usage of partially functional nonvolatile memoryINTEL CORP·Filed 1997·Granted Oct 13, 1998·203 cites·52 claims
- 0389US7401246B2Nibble de-skew method, apparatus, and systemINTEL CORP·Filed 2005·Granted Jul 15, 2008·19 cites·17 claims
- 0489US5623620ASpecial test modes for a page buffer shared resource in a memory deviceINTEL CORP·Filed 1993·Granted Apr 22, 1997·68 cites·29 claims
- 0589US5497355ASynchronous address latching for memory arraysINTEL CORP·Filed 1994·Granted Mar 5, 1996·75 cites·22 claims
- 0688US6958634B2Programmable direct interpolating delay locked loopINTEL CORP·Filed 2003·Granted Oct 25, 2005·38 cites·27 claims
- 0787US7388795B1Modular memory controller clocking architectureINTEL CORP·Filed 2006·Granted Jun 17, 2008·15 cites·20 claims
- 0881US5802552ASystem and method for allocating and sharingpage buffers for a flash memory deviceINTEL CORP·Filed 1997·Granted Sep 1, 1998·96 cites·34 claims
- 0980US7668524B2Clock deskewing method, apparatus, and systemINTEL CORP·Filed 2005·Granted Feb 23, 2010·12 cites·18 claims
- 1079US7109768B2Closed-loop control of driver slew rateINTEL CORP·Filed 2004·Granted Sep 19, 2006·20 cites·19 claims
- 1177US7590789B2Optimizing clock crossing and data path latencyINTEL CORP·Filed 2007·Granted Sep 15, 2009·8 cites·15 claims
- 1274US5835927ASpecial test modes for a page buffer shared resource in a memory deviceINTEL CORP·Filed 1996·Granted Nov 10, 1998·31 cites·14 claims
- 1372US7439788B2Receive clock deskewing method, apparatus, and systemINTEL CORP·Filed 2005·Granted Oct 21, 2008·5 cites·22 claims
- 1467US7555670B2Clocking architecture using a bidirectional clock portINTEL CORP·Filed 2005·Granted Jun 30, 2009·4 cites·18 claims
- 1565US5410544AExternal tester control for flash memoryINTEL CORP·Filed 1993·Granted Apr 25, 1995·24 cites·34 claims
- 1664US8225016B2Even and odd frame combination data path architectureRASHID MAMUN UR·Filed 2007·Granted Jul 17, 2012·4 cites·24 claims
- 1762US7324403B2Latency normalization by balancing early and late clocksINTEL CORP·Filed 2004·Granted Jan 29, 2008·8 cites·30 claims
- 1859US7805627B2Clock synchronization scheme for deskewing operations in a data interfaceINTEL CORP·Filed 2007·Granted Sep 28, 2010·1 cites·10 claims
- 1958US7061224B2Test circuit for delay lock loopsINTEL CORP·Filed 2004·Granted Jun 13, 2006·10 cites·11 claims
- 2058US5586081ASynchronous address latching for memory arraysINTEL CORP·Filed 1995·Granted Dec 17, 1996·31 cites·33 claims
- 2153US7954001B2Nibble de-skew method, apparatus, and systemINTEL CORP·Filed 2008·Granted May 31, 2011·0 cites·20 claims
- 2253US7230464B2Closed-loop delay compensation for driverINTEL CORP·Filed 2004·Granted Jun 12, 2007·7 cites·28 claims
- 2343US2007067594A1Method and apparatus to perform clock crossing on data pathsRASHID MAMUN U·Filed 2005·Application pending·0 cites
- 2439US7684267B2Method and apparatus for memory redundancy in a microprocessorSUN MICROSYSTEMS INC·Filed 2008·Granted Mar 23, 2010·1 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →