Inventor · disambiguated record
Sandeep Brahmadathan
Also filed as: BRAHMADATHAN SANDEEP
22 granted patents·5 pending applications·209 citations·filing 2004–2025
94Inventor score
Top patents by PatentIndex Score
27 records- 0197US12204410B2Integrated error correction code (ECC) and parity protection in memory control circuits for increased memory utilizationAMPERE COMPUTING LLC·Filed 2022·Granted Jan 21, 2025·14 cites·25 claims
- 0295US9811273B1System and method for reliable high-speed data transfer in multiple data rate nonvolatile memoryCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Nov 7, 2017·47 cites·15 claims
- 0394US9886987B1System and method for data-mask training in non-provisioned random access memoryCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Feb 6, 2018·21 cites·20 claims
- 0490US12019565B2Advanced initialization bus (AIB)AMPERE COMPUTING LLC·Filed 2022·Granted Jun 25, 2024·4 cites·18 claims
- 0590US8812898B1System and method for transfer of data between memory with dynamic error recoveryCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Aug 19, 2014·26 cites·25 claims
- 0688US10545866B1Method and system for efficient re-determination of a data valid windowCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jan 28, 2020·10 cites·18 claims
- 0787US9159423B1Robust erase page detection logic for NAND flash memory devicesCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Oct 13, 2015·22 cites·23 claims
- 0887US8904082B1Operation based polling in a memory systemBRAHMADATHAN SANDEEP·Filed 2008·Granted Dec 2, 2014·30 cites·23 claims
- 0986US11934263B2Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilizationAMPERE COMPUTING LLC·Filed 2022·Granted Mar 19, 2024·1 cites·24 claims
- 1085US11481270B1Method and system for sequencing data checks in a packetAMPERE COMPUTING LLC·Filed 2021·Granted Oct 25, 2022·2 cites·18 claims
- 1185US8880980B1System and method for expeditious transfer of data from source to destination in error corrected mannerCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Nov 4, 2014·14 cites·20 claims
- 1283US9471094B1Method of aligning timing of a chip select signal with a cycle of a memory deviceCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Oct 18, 2016·11 cites·20 claims
- 1378US2025231236A1Component die validation built-in self-test (vbist) engineAMPERE COMPUTING LLC·Filed 2025·Application pending·0 cites
- 1475US12314130B2Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilizationAMPERE COMPUTING LLC·Filed 2024·Granted May 27, 2025·0 cites·17 claims
- 1571US12282064B2Component die validation built-in self-test (VBIST) engineAMPERE COMPUTING LLC·Filed 2022·Granted Apr 22, 2025·0 cites·35 claims
- 1670US12411778B2Advanced initialization bus (AIB)AMPERE COMPUTING LLC·Filed 2024·Granted Sep 9, 2025·0 cites·18 claims
- 1767US7941587B2Programmable sequence generator for a flash memory controllerCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted May 10, 2011·4 cites·14 claims
- 1865US11868209B2Method and system for sequencing data checks in a packetAMPERE COMPUTING LLC·Filed 2022·Granted Jan 9, 2024·0 cites·20 claims
- 1959US7739557B2Method, system and program product for autonomous error recovery for memory devicesIBM·Filed 2007·Granted Jun 15, 2010·1 cites·16 claims
- 2055US12159056B2Extending functionality of memory controllers in a processor-based deviceAMPERE COMPUTING LLC·Filed 2022·Granted Dec 3, 2024·0 cites·19 claims
- 2152US7275202B2Method, system and program product for autonomous error recovery for memory devicesIBM·Filed 2004·Granted Sep 25, 2007·2 cites·16 claims
- 2251US12451206B2Extending functionality of memory controllers using a loopback mode for testing in a processor-based deviceAMPERE COMPUTING LLC·Filed 2023·Granted Oct 21, 2025·0 cites·20 claims
- 2341US2009049232A1Execute-in-place implementation for a nand deviceBRAHMADATHAN SANDEEP·Filed 2007·Application pending·0 cites
- 2440US2022405223A1Method and system for data transactions on a communications interfaceAMPERE COMPUTING LLC·Filed 2021·Application pending·0 cites
- 2539US2022407813A1Apparatuses, systems, and methods for implied sequence numbering of transactions in a processor-based systemAMPERE COMPUTING LLC·Filed 2021·Application pending·0 cites
- 2636US10885952B1Memory data transfer and switching sequenceCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jan 5, 2021·0 cites·20 claims
- 2731US2009115451A1Configurable and reusable nand systemBRAHMADATHAN SANDEEP·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →