Inventor · disambiguated record
Stephen T. Quay
Also filed as: QUAY STEPHEN T · QUAY STEPHEN THOMAS
36 granted patents·3 pending applications·1,009 citations·filing 1997–2019
98Inventor score
Technology areasG06F
Top patents by PatentIndex Score
39 records- 0194US6347393B1Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computationIBM·Filed 1999·Granted Feb 12, 2002·230 cites·22 claims
- 0294US6117182AOptimum buffer placement for noise avoidanceIBM·Filed 1998·Granted Sep 12, 2000·229 cites·22 claims
- 0393US7065730B2Porosity aware buffered steiner tree constructionIBM·Filed 2003·Granted Jun 20, 2006·95 cites·8 claims
- 0490US10831971B1Net layer promotion with swap capability in electronic designIBM·Filed 2019·Granted Nov 10, 2020·8 cites·20 claims
- 0588US7299442B2Probabilistic congestion prediction with partial blockagesIBM·Filed 2005·Granted Nov 20, 2007·19 cites·18 claims
- 0687US8365120B2Resolving global coupling timing and slew violations for buffer-dominated designsIBM·Filed 2010·Granted Jan 29, 2013·11 cites·21 claims
- 0787US6401234B1Method and system for re-routing interconnects within an integrated circuit design having blockages and baysIBM·Filed 1999·Granted Jun 4, 2002·132 cites·21 claims
- 0886US8881089B1Physical synthesis optimization with fast metric checkIBM·Filed 2013·Granted Nov 4, 2014·11 cites·14 claims
- 0983US9092591B2Automatic generation of wire tag lists for a metal stackIBM·Filed 2014·Granted Jul 28, 2015·6 cites·19 claims
- 1082US8769468B1Automatic generation of wire tag lists for a metal stackIBM·Filed 2013·Granted Jul 1, 2014·6 cites·23 claims
- 1182US8640075B2Early design cycle optimzationALPERT CHARLES JAY·Filed 2012·Granted Jan 28, 2014·6 cites·19 claims
- 1282US7484199B2Buffer insertion to reduce wirelength in VLSI circuitsIBM·Filed 2006·Granted Jan 27, 2009·9 cites·14 claims
- 1381US10839122B1Automatic layer trait generation and promotion cost computationIBM·Filed 2019·Granted Nov 17, 2020·3 cites·20 claims
- 1480US6591411B2Apparatus and method for determining buffered steiner trees for complex circuitsIBM·Filed 2001·Granted Jul 8, 2003·30 cites·45 claims
- 1579US9875326B2Addressing coupled noise-based violations with buffering in a batch environmentIBM·Filed 2015·Granted Jan 23, 2018·3 cites·14 claims
- 1679US7448007B2Slew constrained minimum cost bufferingIBM·Filed 2006·Granted Nov 4, 2008·9 cites·4 claims
- 1777US7895557B2Concurrent buffering and layer assignment in integrated circuit layoutIBM·Filed 2008·Granted Feb 22, 2011·10 cites·2 claims
- 1877US7127696B2Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density managementIBM·Filed 2003·Granted Oct 24, 2006·26 cites·25 claims
- 1976US7676780B2Techniques for super fast buffer insertionIBM·Filed 2007·Granted Mar 9, 2010·6 cites·6 claims
- 2074US9038009B2Early design cycle optimizationIBM·Filed 2013·Granted May 19, 2015·3 cites·9 claims
- 2171US6560752B1Apparatus and method for buffer library selection for use in buffer insertionIBM·Filed 2000·Granted May 6, 2003·16 cites·47 claims
- 2268US8386985B2Timing driven routing in integrated circuit designIBM·Filed 2011·Granted Feb 26, 2013·2 cites·20 claims
- 2368US7890905B2Slew constrained minimum cost bufferingIBM·Filed 2008·Granted Feb 15, 2011·4 cites·8 claims
- 2466US10503841B2Integrated circuit buffering solutions considering sink delaysIBM·Filed 2019·Granted Dec 10, 2019·0 cites·20 claims
- 2566US10496764B2Integrated circuit buffering solutions considering sink delaysIBM·Filed 2019·Granted Dec 3, 2019·0 cites·20 claims
- 2664US6898774B2Buffer insertion with adaptive blockage avoidanceIBM·Filed 2002·Granted May 24, 2005·10 cites·27 claims
- 2762US10372836B2Integrated circuit buffering solutions considering sink delaysIBM·Filed 2017·Granted Aug 6, 2019·0 cites·19 claims
- 2862US10372837B2Integrated circuit buffering solutions considering sink delaysIBM·Filed 2018·Granted Aug 6, 2019·0 cites·1 claims
- 2962US7137081B2Method and apparatus for performing density-biased buffer insertion in an integrated circuit designIBM·Filed 2003·Granted Nov 14, 2006·10 cites·6 claims
- 3061US10346558B2Integrated circuit buffering solutions considering sink delaysIBM·Filed 2017·Granted Jul 9, 2019·0 cites·20 claims
- 3161US6915496B2Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation techniqueIBM·Filed 2002·Granted Jul 5, 2005·10 cites·19 claims
- 3259US7392493B2Techniques for super fast buffer insertionIBM·Filed 2004·Granted Jun 24, 2008·5 cites·12 claims
- 3358US6360350B1Method and system for performing circuit analysis on an integrated-circuit design having design data available in different formsIBM·Filed 1997·Granted Mar 19, 2002·39 cites·12 claims
- 3458US6044209AMethod and system for segmenting wires prior to buffer insertionIBM·Filed 1997·Granted Mar 28, 2000·33 cites·20 claims
- 3554US2009064080A1Buffer insertion to reduce wirelength in vlsi circuitsALPERT CHARLES J·Filed 2008·Application pending·0 cites
- 3653US2009013299A1Buffer insertion to reduce wirelength in vlsi circuitsALPERT CHARLES J·Filed 2008·Application pending·0 cites
- 3748US6230302B1Method and system for performing timing analysis on an integrated circuit designIBM·Filed 1998·Granted May 8, 2001·20 cites·9 claims
- 3842US2007283301A1System and Method of Eliminating Electrical ViolationsKARANDIKAR ARVIND K·Filed 2006·Application pending·0 cites
- 3934US5991521AMethod and system of checking for open circuit connections within an integrated-circuit design represented by a hierarchical data structureIBM·Filed 1997·Granted Nov 23, 1999·8 cites·12 claims
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