Inventor · disambiguated record
John Stephen Muhich
Also filed as: MUHICH JOHN S · MUHICH JOHN STEPHEN
50 granted patents·1,514 citations·filing 1985–1999
99Inventor score
Top patents by PatentIndex Score
50 records- 0185US5611058ASystem and method for transferring information between multiple busesIBM·Filed 1996·Granted Mar 11, 1997·126 cites·23 claims
- 0284US6021485AForwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matchingIBM·Filed 1997·Granted Feb 1, 2000·113 cites·24 claims
- 0384US5437017AMethod and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing systemIBM·Filed 1992·Granted Jul 25, 1995·109 cites·14 claims
- 0472US5887161AIssuing instructions in a processor supporting out-of-order executionIBM·Filed 1997·Granted Mar 23, 1999·62 cites·20 claims
- 0571US5870582AMethod and apparatus for completion of non-interruptible instructions before the instruction is dispatchedIBM·Filed 1997·Granted Feb 9, 1999·60 cites·17 claims
- 0671US5463739AApparatus for vetoing reallocation requests during a data transfer based on data bus latency and the number of received reallocation requests below a thresholdIBM·Filed 1992·Granted Oct 31, 1995·55 cites·15 claims
- 0769US6021512AData processing system having memory sub-array redundancy and method thereforIBM·Filed 1996·Granted Feb 1, 2000·28 cites·14 claims
- 0869US5931957ASupport for out-of-order execution of loads and stores in a processorIBM·Filed 1997·Granted Aug 3, 1999·57 cites·1 claims
- 0969US4742350ASoftware managed video synchronization generationIBM·Filed 1986·Granted May 3, 1988·26 cites·13 claims
- 1068US5729501AHigh Speed SRAM with or-gate senseIBM·Filed 1995·Granted Mar 17, 1998·27 cites·15 claims
- 1167US5623450AConditional recharge for dynamic logicIBM·Filed 1995·Granted Apr 22, 1997·22 cites·7 claims
- 1266US5872950AMethod and apparatus for managing register renaming including a wraparound array and an indication of rename entry agesIBM·Filed 1997·Granted Feb 16, 1999·49 cites·4 claims
- 1365US5913048ADispatching instructions in a processor supporting out-of-order executionIBM·Filed 1997·Granted Jun 15, 1999·45 cites·16 claims
- 1465US5802571AApparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memoryIBM·Filed 1996·Granted Sep 1, 1998·44 cites·16 claims
- 1565US5706464AMethod and system for achieving atomic memory references in a multilevel cache data processing systemIBM·Filed 1996·Granted Jan 6, 1998·48 cites·6 claims
- 1663US6412051B1System and method for controlling a memory array in an information handling systemIBM·Filed 1996·Granted Jun 25, 2002·21 cites·9 claims
- 1762US6098167AApparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order executionIBM·Filed 1997·Granted Aug 1, 2000·40 cites·16 claims
- 1862US5442766AMethod and system for distributed instruction address translation in a multiscalar data processing systemIBM·Filed 1992·Granted Aug 15, 1995·40 cites·10 claims
- 1961US5668761AFast read domino SRAMIBM·Filed 1995·Granted Sep 16, 1997·20 cites·7 claims
- 2059US4706074ACursor circuit for a dual port memoryIBM·Filed 1986·Granted Nov 10, 1987·22 cites·10 claims
- 2158US5500950AData processor with speculative data transfer and address-free retryMOTOROLA INC·Filed 1993·Granted Mar 19, 1996·31 cites·13 claims
- 2257US6389585B1Method and system for building a multiprocessor data processing systemIBM·Filed 1999·Granted May 14, 2002·32 cites·15 claims
- 2357US5949262AMethod and apparatus for coupled phase locked loopsIBM·Filed 1998·Granted Sep 7, 1999·36 cites·10 claims
- 2456US6014047AMethod and apparatus for phase rotation in a phase locked loopIBM·Filed 1998·Granted Jan 11, 2000·31 cites·8 claims
- 2555US5640518AAddition of pre-last transfer acknowledge signal to bus interface to eliminate data bus turnaround on consecutive read and write tenures and to allow burst transfers of unknown lengthIBM·Filed 1996·Granted Jun 17, 1997·32 cites·11 claims
- 2654US6266767B1Apparatus and method for facilitating out-of-order execution of load instructionsIBM·Filed 1999·Granted Jul 24, 2001·28 cites·20 claims
- 2752US6070238AMethod and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instructionIBM·Filed 1997·Granted May 30, 2000·25 cites·14 claims
- 2852US5758120AMethod and system for increased system memory concurrency in a multi-processor computer system utilizing concurrent access of reference and change bitsINTERNATIIONAL BUSINESS MACHIN·Filed 1996·Granted May 26, 1998·28 cites·8 claims
- 2951US6002285ACircuitry and method for latching informationIBM·Filed 1996·Granted Dec 14, 1999·12 cites·14 claims
- 3050US5870612AMethod and apparatus for condensed history bufferIBM·Filed 1996·Granted Feb 9, 1999·22 cites·12 claims
- 3149US5860014AMethod and apparatus for improved recovery of processor state using history bufferIBM·Filed 1996·Granted Jan 12, 1999·21 cites·14 claims
- 3247US5848283AMethod and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronizationIBM·Filed 1993·Granted Dec 8, 1998·23 cites·12 claims
- 3346US5812418ACache sub-array method and apparatus for use in microprocessor integrated circuitsIBM·Filed 1996·Granted Sep 22, 1998·17 cites·6 claims
- 3446US5796998AApparatus and method for performing branch target address calculation and branch prediciton in parallel in an information handling systemIBM·Filed 1996·Granted Aug 18, 1998·18 cites·22 claims
- 3544US5615160AMinimal recharge overhead circuit for domino SRAM structuresIBM·Filed 1995·Granted Mar 25, 1997·9 cites·6 claims
- 3643US5918044AApparatus and method for instruction fetching using a multi-port instruction cache directoryIBM·Filed 1996·Granted Jun 29, 1999·15 cites·41 claims
- 3743US4740927ABit addressable multidimensional arrayIBM·Filed 1985·Granted Apr 26, 1988·8 cites·6 claims
- 3842US5864341AInstruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwardingIBM·Filed 1996·Granted Jan 26, 1999·15 cites·6 claims
- 3942US5532947ACombined decoder/adder circuit which provides improved access speed to a cacheIBM·Filed 1995·Granted Jul 2, 1996·14 cites·10 claims
- 4041US6021467AApparatus and method for processing multiple cache misses to a single cache lineIBM·Filed 1996·Granted Feb 1, 2000·13 cites·16 claims
- 4139US5784604AMethod and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purgingIBM·Filed 1992·Granted Jul 21, 1998·11 cites·16 claims
- 4238US6055557AAdder circuit and method thereforIBM·Filed 1997·Granted Apr 25, 2000·10 cites·19 claims
- 4338US5870592AClock generation apparatus and method for CMOS microprocessors using a differential saw oscillatorIBM·Filed 1996·Granted Feb 9, 1999·7 cites·8 claims
- 4438US5742784ASystem for reordering of instructions before placement into cache to reduce dispatch latencyIBM·Filed 1995·Granted Apr 21, 1998·10 cites·11 claims
- 4537US6079002ADynamic expansion of execution pipeline stagesIBM·Filed 1997·Granted Jun 20, 2000·9 cites·27 claims
- 4636US4763251AMerge and copy bit block transfer implementationIBM·Filed 1986·Granted Aug 9, 1988·10 cites·15 claims
- 4735US5689198ACircuitry and method for gating informationIBM·Filed 1995·Granted Nov 18, 1997·4 cites·5 claims
- 4835US5668525AComparator circuit using two bit to four bit encoderIBM·Filed 1996·Granted Sep 16, 1997·8 cites·27 claims
- 4930US6167500AMechanism for queuing store data and method thereforIBM·Filed 1998·Granted Dec 26, 2000·1 cites·35 claims
- 5030US5822752AMethod and apparatus for fast parallel determination of queue entriesIBM·Filed 1996·Granted Oct 13, 1998·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →