Inventor · disambiguated record
Harry Barowski
Also filed as: BAROWSKI HARRY · BAROWSKI HARRY S · BAROWSKI HARRY STEFAN
60 granted patents·5 pending applications·328 citations·filing 2001–2022
98Inventor score
Top patents by PatentIndex Score
65 records- 0196US9501603B2Integrated circuit design changes using through-silicon viasIBM·Filed 2014·Granted Nov 22, 2016·40 cites·10 claims
- 0293US9406375B1Write address synchronization in 2 read/1write SRAM arraysIBM·Filed 2015·Granted Aug 2, 2016·16 cites·12 claims
- 0393US8427833B2Thermal power plane for integrated circuitsBAROWSKI HARRY·Filed 2010·Granted Apr 23, 2013·19 cites·24 claims
- 0492US7694112B2Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computationIBM·Filed 2008·Granted Apr 6, 2010·37 cites·2 claims
- 0590US8375345B1Soft-bounded hierarchical synthesisIBM·Filed 2012·Granted Feb 12, 2013·21 cites·18 claims
- 0690US8253234B2Optimized semiconductor packaging in a three-dimensional stackBAROWSKI HARRY·Filed 2010·Granted Aug 28, 2012·11 cites·6 claims
- 0786US9928329B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2016·Granted Mar 27, 2018·3 cites·20 claims
- 0886US9910948B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2016·Granted Mar 6, 2018·3 cites·16 claims
- 0985US11501196B2Qubit tuning by magnetic fields in superconductorsIBM·Filed 2018·Granted Nov 15, 2022·4 cites·20 claims
- 1085US8805132B2Integrated circuit package connected to a data transmission mediumBAROWSKI HARRY·Filed 2011·Granted Aug 12, 2014·8 cites·14 claims
- 1184US10242140B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2017·Granted Mar 26, 2019·2 cites·18 claims
- 1284US10235487B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2017·Granted Mar 19, 2019·2 cites·9 claims
- 1384US8245065B2Power gating processor execution units when number of instructions issued per cycle falls below threshold and are independent until instruction queue is fullNIGGEMEIER TIM·Filed 2009·Granted Aug 14, 2012·17 cites·11 claims
- 1484US7509511B1Reducing register file leakage current within a processorIBM·Filed 2008·Granted Mar 24, 2009·14 cites·1 claims
- 1583US8316335B2Multistage, hybrid synthesis processing facilitating integrated circuit layoutBAROWSKI HARRY·Filed 2010·Granted Nov 20, 2012·10 cites·20 claims
- 1683US7502918B1Method and system for data dependent performance increment and power reductionIBM·Filed 2008·Granted Mar 10, 2009·13 cites·1 claims
- 1782US6968476B2Checkpointing a superscalar, out-of-order processor for error recoveryIBM·Filed 2002·Granted Nov 22, 2005·33 cites·13 claims
- 1880US10223491B2Integrated circuit design changes using through-silicon viasIBM·Filed 2017·Granted Mar 5, 2019·2 cites·15 claims
- 1979US9569580B2Integrated circuit design changes using through-silicon viasIBM·Filed 2015·Granted Feb 14, 2017·2 cites·4 claims
- 2079US8476112B2Optimized semiconductor packaging in a three-dimensional stackBAROWSKI HARRY·Filed 2012·Granted Jul 2, 2013·4 cites·8 claims
- 2179US8405998B2Heat sink integrated power delivery and distribution for integrated circuitsBAROWSKI HARRY·Filed 2010·Granted Mar 26, 2013·5 cites·24 claims
- 2277US10956644B2Integrated circuit design changes using through-silicon viasIBM·Filed 2019·Granted Mar 23, 2021·1 cites·20 claims
- 2377US8578196B2Zero indication forwarding for floating point unit power reductionBAROWSKI HARRY S·Filed 2012·Granted Nov 5, 2013·3 cites·14 claims
- 2475US10223489B2Placement clustering-based white space reservationIBM·Filed 2016·Granted Mar 5, 2019·2 cites·20 claims
- 2574US8989532B2Integrated circuit package connected to an optical data transmission medium using a coolantBAROWSKI HARRY·Filed 2011·Granted Mar 24, 2015·3 cites·16 claims
- 2674US7849428B2Formally deriving a minimal clock-gating schemeIBM·Filed 2008·Granted Dec 7, 2010·7 cites·20 claims
- 2773US9658853B2Techniques for increasing instruction issue rate and reducing latency in an out-of order processorGLOBALFOUNDRIES INC·Filed 2014·Granted May 23, 2017·3 cites·19 claims
- 2873US8421500B2Integrated circuit with stacked computational units and configurable through viasBAROWSKI HARRY S·Filed 2010·Granted Apr 16, 2013·3 cites·23 claims
- 2973US6986027B2Universal load address/value prediction using stride-based pattern history and last-value prediction in a two-level table schemeIBM·Filed 2001·Granted Jan 10, 2006·19 cites·9 claims
- 3071US10593420B2Testing content addressable memory and random access memoryIBM·Filed 2018·Granted Mar 17, 2020·2 cites·11 claims
- 3171US8806253B2Power down of execution units for issued instruction accumulation when issue rate of instructions falls below threshold and at least two are independentNIGGEMEIER TIM·Filed 2012·Granted Aug 12, 2014·3 cites·11 claims
- 3270US10170199B2Testing content addressable memory and random access memoryIBM·Filed 2018·Granted Jan 1, 2019·2 cites·1 claims
- 3370US9395996B2Pipelining out-of-order instructionsIBM·Filed 2013·Granted Jul 19, 2016·2 cites·17 claims
- 3469US10079070B2Testing content addressable memory and random access memoryIBM·Filed 2016·Granted Sep 18, 2018·2 cites·9 claims
- 3569US9733945B2Pipelining out-of-order instructionsIBM·Filed 2016·Granted Aug 15, 2017·1 cites·14 claims
- 3669US9684759B2De-coupling capacitance placementIBM·Filed 2015·Granted Jun 20, 2017·1 cites·13 claims
- 3768US9679099B2De-coupling capacitance placementIBM·Filed 2015·Granted Jun 13, 2017·1 cites·20 claims
- 3867US10534884B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2019·Granted Jan 14, 2020·0 cites·20 claims
- 3966US9437285B1Write address synchronization in 2 read/1write SRAM arraysIBM·Filed 2016·Granted Sep 6, 2016·2 cites·8 claims
- 4065US10417366B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2018·Granted Sep 17, 2019·0 cites·20 claims
- 4165US10366191B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2018·Granted Jul 30, 2019·0 cites·11 claims
- 4265US10333508B2Cross bar switch structure for highly congested environmentsIBM·Filed 2017·Granted Jun 25, 2019·1 cites·20 claims
- 4365US8255726B2Zero indication forwarding for floating point unit power reductionBAROWSKI HARRY S·Filed 2008·Granted Aug 28, 2012·3 cites·14 claims
- 4463US9412682B2Through-silicon via access device for integrated circuitsIBM·Filed 2014·Granted Aug 9, 2016·1 cites·11 claims
- 4560US11881853B2True complement dynamic circuit and method for combining binary dataIBM·Filed 2022·Granted Jan 23, 2024·0 cites·24 claims
- 4656US10169519B2Area sharing between multiple large block synthesis (LBS) blocksIBM·Filed 2018·Granted Jan 1, 2019·0 cites·17 claims
- 4755US9058461B2Transferring heat through an optical layer of integrated circuitryIBM·Filed 2013·Granted Jun 16, 2015·0 cites·12 claims
- 4853US8984314B2Charge recycling between power domains of integrated circuitsIBM·Filed 2013·Granted Mar 17, 2015·0 cites·6 claims
- 4952US11043938B2Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal featureIBM·Filed 2019·Granted Jun 22, 2021·0 cites·19 claims
- 5052US9946830B2Area sharing between multiple large block synthesis (LBS) blocksIBM·Filed 2016·Granted Apr 17, 2018·0 cites·20 claims
Showing the top 50 of 65 patent records by PatentIndex Score.
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