Inventor · disambiguated record
Michael K. Gschwind
Also filed as: GSCHWIND MICHAEL · GSCHWIND MICHAEL K · GSCHWIND MICHAEL KARL
836 granted patents·46 pending applications·5,509 citations·filing 1999–2021
99Inventor score
Files withIBM773GSCHWIND MICHAEL K32BRADBURY JONATHAN D14EICHENBERGER ALEXANDRE E14GSCHWIND MICHAEL KARL11
Top patents by PatentIndex Score
882 records- 0198US9760494B2Hybrid tracking of transaction read and write setsIBM·Filed 2015·Granted Sep 12, 2017·16 cites·9 claims
- 0298US9348616B2Linking a function with dual entry pointsIBM·Filed 2014·Granted May 24, 2016·56 cites·8 claims
- 0398US9311093B2Prefix computer instruction for compatibly extending instruction functionalityIBM·Filed 2013·Granted Apr 12, 2016·75 cites·14 claims
- 0498US9250875B1Table of contents pointer value save and restore placeholder positioningIBM·Filed 2014·Granted Feb 2, 2016·54 cites·8 claims
- 0598US9250881B1Selection of an entry point of a function having multiple entry pointsIBM·Filed 2014·Granted Feb 2, 2016·52 cites·11 claims
- 0698US9218170B1Managing table of contents pointer value savesIBM·Filed 2015·Granted Dec 22, 2015·33 cites·8 claims
- 0798US6839828B2SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing modeIBM·Filed 2001·Granted Jan 4, 2005·248 cites·21 claims
- 0897US10209972B2Executing optimized local entry pointsIBM·Filed 2017·Granted Feb 19, 2019·19 cites·8 claims
- 0997US9952844B1Executing optimized local entry points and function call sitesIBM·Filed 2016·Granted Apr 24, 2018·23 cites·14 claims
- 1097US9727337B2Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registersIBM·Filed 2012·Granted Aug 8, 2017·48 cites·10 claims
- 1197US9619383B2Dynamic predictor for coalescing memory transactionsIBM·Filed 2015·Granted Apr 11, 2017·18 cites·17 claims
- 1297US9569338B1Fingerprint-initiated trace extractionIBM·Filed 2015·Granted Feb 14, 2017·22 cites·20 claims
- 1397US9535696B1Instruction to cancel outstanding cache prefetchesIBM·Filed 2016·Granted Jan 3, 2017·17 cites·20 claims
- 1497US9384130B2Rewriting symbol address initialization sequencesIBM·Filed 2014·Granted Jul 5, 2016·44 cites·13 claims
- 1597US9354885B1Selective suppression of instruction cache-related directory accessIBM·Filed 2016·Granted May 31, 2016·22 cites·19 claims
- 1697US9329850B2Relocation of instructions that use relative addressingIBM·Filed 2014·Granted May 3, 2016·40 cites·17 claims
- 1797US9244854B2Transparent code patching including updating of address translation structuresIBM·Filed 2014·Granted Jan 26, 2016·39 cites·10 claims
- 1897US9110675B1Usage of TOC register as application registerIBM·Filed 2014·Granted Aug 18, 2015·39 cites·8 claims
- 1997US9075636B2Optimizing subroutine calls based on architecture level of called subroutineIBM·Filed 2013·Granted Jul 7, 2015·39 cites·4 claims
- 2097US9021511B1Runtime management of TOC pointer save and restore commandsIBM·Filed 2014·Granted Apr 28, 2015·37 cites·8 claims
- 2197US8010953B2Method for compiling scalar code for a single instruction multiple data (SIMD) execution engineIBM·Filed 2006·Granted Aug 30, 2011·60 cites·1 claims
- 2296US9971713B2Multi-petascale highly efficient parallel supercomputerGLOBALFOUNDRIES INC·Filed 2015·Granted May 15, 2018·30 cites·14 claims
- 2396US9720661B2Selectively controlling use of extended mode featuresIBM·Filed 2014·Granted Aug 1, 2017·34 cites·15 claims
- 2496US9720662B2Selectively controlling use of extended mode featuresIBM·Filed 2014·Granted Aug 1, 2017·35 cites·9 claims
- 2596US9606855B1Caller protected stack return address in a hardware managed stack architectureIBM·Filed 2016·Granted Mar 28, 2017·16 cites·20 claims
- 2696US9582274B1Architected store and verify guard word instructionsIBM·Filed 2016·Granted Feb 28, 2017·16 cites·12 claims
- 2796US9514006B1Transaction tracking within a microprocessorIBM·Filed 2015·Granted Dec 6, 2016·22 cites·20 claims
- 2896US9471313B1Flushing speculative instruction processingIBM·Filed 2015·Granted Oct 18, 2016·22 cites·19 claims
- 2996US9384133B2Synchronizing updates of page table status indicators and performing bulk operationsIBM·Filed 2014·Granted Jul 5, 2016·25 cites·20 claims
- 3096US9244782B2Salvaging hardware transactionsIBM·Filed 2015·Granted Jan 26, 2016·13 cites·6 claims
- 3196US9244781B2Salvaging hardware transactionsIBM·Filed 2015·Granted Jan 26, 2016·16 cites·6 claims
- 3296US9146715B1Suppression of table of contents save actionsIBM·Filed 2014·Granted Sep 29, 2015·35 cites·11 claims
- 3396US9081501B2Multi-petascale highly efficient parallel supercomputerASAAD SAMEH·Filed 2011·Granted Jul 14, 2015·115 cites·41 claims
- 3496US9021512B1Runtime management of TOC pointer save and restore commandsIBM·Filed 2014·Granted Apr 28, 2015·35 cites·14 claims
- 3596US8188761B2Soft error detection for latchesFLEISCHER BRUCE M·Filed 2011·Granted May 29, 2012·18 cites·16 claims
- 3696US8108846B2Compiling scalar code for a single instruction multiple data (SIMD) execution engineGSCHWIND MICHAEL K·Filed 2008·Granted Jan 31, 2012·46 cites·11 claims
- 3796US7977965B1Soft error detection for latchesIBM·Filed 2010·Granted Jul 12, 2011·20 cites·14 claims
- 3896US7877582B2Multi-addressable register fileIBM·Filed 2008·Granted Jan 25, 2011·68 cites·19 claims
- 3996US6349361B1Methods and apparatus for reordering and renaming memory references in a multiprocessor computer systemIBM·Filed 2000·Granted Feb 19, 2002·199 cites·25 claims
- 4095US9836291B1Reconfiguration of address space based on loading short pointer mode applicationIBM·Filed 2016·Granted Dec 5, 2017·11 cites·17 claims
- 4195US9594576B2Architectural mode configurationIBM·Filed 2014·Granted Mar 14, 2017·17 cites·8 claims
- 4295US9576128B1Interlinking routines with differing protections using stack indicatorsIBM·Filed 2016·Granted Feb 21, 2017·12 cites·17 claims
- 4395US9514301B1Interlinking modules with differing protections using stack indicatorsIBM·Filed 2016·Granted Dec 6, 2016·14 cites·11 claims
- 4495US9495237B1Detection of corruption of call stacksIBM·Filed 2016·Granted Nov 15, 2016·17 cites·20 claims
- 4595US9329869B2Prefix computer instruction for compatibily extending instruction functionalityGSCHWIND MICHAEL K·Filed 2011·Granted May 3, 2016·26 cites·7 claims
- 4695US9298626B2Managing high-conflict cache lines in transactional memory computing environmentsGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 29, 2016·25 cites·17 claims
- 4795US9244663B1Managing table of contents pointer value savesIBM·Filed 2014·Granted Jan 26, 2016·22 cites·12 claims
- 4895US9218168B1Suppression of table of contents save actionsIBM·Filed 2014·Granted Dec 22, 2015·23 cites·9 claims
- 4995US9158573B2Dynamic predictor for coalescing memory transactionsIBM·Filed 2013·Granted Oct 13, 2015·23 cites·18 claims
- 5095US9063759B2Optimizing subroutine calls based on architecture level of called subroutineGSCHWIND MICHAEL K·Filed 2012·Granted Jun 23, 2015·22 cites·13 claims
Showing the top 50 of 882 patent records by PatentIndex Score.
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