Assignee
GSCHWIND MICHAEL K
US·26 granted patents·6 pending applications·220 citations·filing 2005–2012
Top patents by PatentIndex Score
32 records- 0196US8108846B2Compiling scalar code for a single instruction multiple data (SIMD) execution engineGSCHWIND MICHAEL K·Filed 2008·Granted Jan 31, 2012·46 cites·11 claims
- 0295US9329869B2Prefix computer instruction for compatibily extending instruction functionalityGSCHWIND MICHAEL K·Filed 2011·Granted May 3, 2016·26 cites·7 claims
- 0395US9063759B2Optimizing subroutine calls based on architecture level of called subroutineGSCHWIND MICHAEL K·Filed 2012·Granted Jun 23, 2015·22 cites·13 claims
- 0493US8495607B2Performing aggressive code optimization with an ability to rollback changes made by the aggressive optimizationsGSCHWIND MICHAEL K·Filed 2010·Granted Jul 23, 2013·20 cites·25 claims
- 0592US8984042B2Mixed precision estimate instruction computing narrow precision result for wide precision inputsGSCHWIND MICHAEL K·Filed 2012·Granted Mar 17, 2015·16 cites·9 claims
- 0685US9280348B2Decode time instruction optimization for load reserve and store conditional sequencesGSCHWIND MICHAEL K·Filed 2012·Granted Mar 8, 2016·7 cites·11 claims
- 0785US9280347B2Transforming non-contiguous instruction specifiers to contiguous instruction specifiersGSCHWIND MICHAEL K·Filed 2012·Granted Mar 8, 2016·7 cites·19 claims
- 0885US8756591B2Generating compiled code that indicates register livenessGSCHWIND MICHAEL K·Filed 2011·Granted Jun 17, 2014·7 cites·18 claims
- 0985US8327344B2Array reference safety analysis in the presence of loops with conditional control flowGSCHWIND MICHAEL K·Filed 2008·Granted Dec 4, 2012·14 cites·16 claims
- 1084US8423983B2Generating and executing programs for a floating point single instruction multiple data instruction set architectureGSCHWIND MICHAEL K·Filed 2008·Granted Apr 16, 2013·13 cites·20 claims
- 1181US9690583B2Exploiting an architected list-use operand indication in a computer system operand resource poolGSCHWIND MICHAEL K·Filed 2011·Granted Jun 27, 2017·5 cites·8 claims
- 1281US8972788B2Ticket consolidationGSCHWIND MICHAEL K·Filed 2012·Granted Mar 3, 2015·6 cites·29 claims
- 1378US10078515B2Tracking operand liveness information in a computer system and performing function based on the liveness informationGSCHWIND MICHAEL K·Filed 2011·Granted Sep 18, 2018·4 cites·7 claims
- 1476US9286072B2Using register last use infomation to perform decode-time computer instruction optimizationGSCHWIND MICHAEL K·Filed 2011·Granted Mar 15, 2016·3 cites·8 claims
- 1575US9513915B2Instruction merging optimizationGSCHWIND MICHAEL K·Filed 2012·Granted Dec 6, 2016·3 cites·13 claims
- 1675US9323530B2Caching optimized internal instructions in loop bufferGSCHWIND MICHAEL K·Filed 2012·Granted Apr 26, 2016·3 cites·8 claims
- 1775US9292291B2Instruction merging optimizationGSCHWIND MICHAEL K·Filed 2012·Granted Mar 22, 2016·3 cites·11 claims
- 1874US9354888B2Performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence cachingGSCHWIND MICHAEL K·Filed 2012·Granted May 31, 2016·3 cites·3 claims
- 1970US9697002B2Computer instructions for activating and deactivating operandsGSCHWIND MICHAEL K·Filed 2011·Granted Jul 4, 2017·2 cites·8 claims
- 2070US9354874B2Scalable decode-time instruction sequence optimization of dependent instructionsGSCHWIND MICHAEL K·Filed 2011·Granted May 31, 2016·2 cites·8 claims
- 2169US8468531B2Method and apparatus for efficient inter-thread synchronization for helper threadsGSCHWIND MICHAEL K·Filed 2010·Granted Jun 18, 2013·2 cites·16 claims
- 2268US8453161B2Method and apparatus for efficient helper thread state initialization using inter-thread register copyGSCHWIND MICHAEL K·Filed 2010·Granted May 28, 2013·2 cites·21 claims
- 2364US9727336B2Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registersGSCHWIND MICHAEL K·Filed 2011·Granted Aug 8, 2017·1 cites·16 claims
- 2464US9411585B2Multi-addressable register files and format conversions associated therewithGSCHWIND MICHAEL K·Filed 2011·Granted Aug 9, 2016·1 cites·16 claims
- 2559US8458677B2Generating code adapted for interlinking legacy scalar code and extended vector codeGSCHWIND MICHAEL K·Filed 2009·Granted Jun 4, 2013·1 cites·19 claims
- 2659US8127078B2High performance unaligned cache accessGSCHWIND MICHAEL K·Filed 2009·Granted Feb 28, 2012·1 cites·25 claims
- 2753US2007186077A1System and Method for Executing Instructions Utilizing a Preferred Slot Alignment MechanismGSCHWIND MICHAEL K·Filed 2006·Application pending·0 cites
- 2851US2007038984A1Methods for generating code for an architecture encoding an extended register specificationGSCHWIND MICHAEL K·Filed 2006·Application pending·0 cites
- 2949US2013086364A1Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand Last-User InformationGSCHWIND MICHAEL K·Filed 2011·Application pending·0 cites
- 3043US2006155955A1SIMD-RISC processor moduleGSCHWIND MICHAEL K·Filed 2005·Application pending·0 cites
- 3143US2006236036A1Method and apparatus for predictive scheduling of memory accesses based on reference localityGSCHWIND MICHAEL K·Filed 2005·Application pending·0 cites
- 3243US2007050592A1Method and apparatus for accessing misaligned data streamsGSCHWIND MICHAEL K·Filed 2005·Application pending·0 cites
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