Inventor · disambiguated record
David S. Levitan
Also filed as: LEVITAN DAVID S · LEVITAN DAVID STEPHEN
73 granted patents·8 pending applications·1,047 citations·filing 1993–2019
99Inventor score
Top patents by PatentIndex Score
81 records- 0196US7487334B2Branch encoding before instruction cache writeIBM·Filed 2005·Granted Feb 3, 2009·61 cites·1 claims
- 0296US7269715B2Instruction grouping history on fetch-side dispatch group formationIBM·Filed 2005·Granted Sep 11, 2007·62 cites·14 claims
- 0394US7809933B2System and method for optimizing branch logic for handling hard to predict indirect branchesIBM·Filed 2007·Granted Oct 5, 2010·49 cites·20 claims
- 0493US9069563B2Reducing store-hit-loads in an out-of-order processorKONIGSBURG BRIAN R·Filed 2011·Granted Jun 30, 2015·32 cites·20 claims
- 0593US7657783B2Apparatus and computer program product for testing ability to recover from cache directory errorsIBM·Filed 2008·Granted Feb 2, 2010·28 cites·12 claims
- 0692US9983878B2Branch prediction using multiple versions of history dataIBM·Filed 2014·Granted May 29, 2018·12 cites·16 claims
- 0792US7783870B2Branch target address cacheIBM·Filed 2007·Granted Aug 24, 2010·30 cites·17 claims
- 0890US8943299B2Operating a stack of information in an information handling systemEKANADHAM KATTAMURI·Filed 2010·Granted Jan 27, 2015·17 cites·23 claims
- 0986US10078514B2Techniques for dynamic sequential instruction prefetchingIBM·Filed 2016·Granted Sep 18, 2018·4 cites·20 claims
- 1084US8131976B2Tracking effective addresses in an out-of-order processorDOING RICHARD W·Filed 2009·Granted Mar 6, 2012·18 cites·22 claims
- 1184US7254700B2Fencing off instruction buffer until re-circulation of rejected preceding and branch instructions to avoid mispredict flushIBM·Filed 2005·Granted Aug 7, 2007·14 cites·20 claims
- 1282US9715411B2Techniques for mapping logical threads to physical threads in a simultaneous multithreading data processing systemIBM·Filed 2014·Granted Jul 25, 2017·6 cites·20 claims
- 1381US5367703AMethod and system for enhanced branch history prediction accuracy in a superscalar processor systemIBM·Filed 1993·Granted Nov 22, 1994·91 cites·10 claims
- 1480US7877586B2Branch target address cache selectively applying a delayed hitIBM·Filed 2008·Granted Jan 25, 2011·10 cites·13 claims
- 1580US7689816B2Branch prediction with partially folded global history vector for reduced XOR operation timeIBM·Filed 2008·Granted Mar 30, 2010·10 cites·12 claims
- 1680US7032097B2Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cacheIBM·Filed 2003·Granted Apr 18, 2006·28 cites·24 claims
- 1779US10037207B2Power management of branch predictors in a computer processorIBM·Filed 2016·Granted Jul 31, 2018·2 cites·7 claims
- 1878US9996351B2Power management of branch predictors in a computer processorIBM·Filed 2016·Granted Jun 12, 2018·2 cites·10 claims
- 1978US8635621B2Method and apparatus to implement software to hardware thread priorityLEVITAN DAVID STEPHEN·Filed 2008·Granted Jan 21, 2014·12 cites·1 claims
- 2077US7890738B2Method and logical apparatus for managing processing system resource use for speculative executionIBM·Filed 2005·Granted Feb 15, 2011·8 cites·21 claims
- 2176US9442736B2Techniques for selecting a predicted indirect branch address from global and local cachesGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 13, 2016·4 cites·20 claims
- 2276US7120784B2Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environmentIBM·Filed 2003·Granted Oct 10, 2006·23 cites·28 claims
- 2374US5796758ASelf-checking content-addressable memory and method of operation for detecting multiple selected word linesIBM·Filed 1996·Granted Aug 18, 1998·65 cites·6 claims
- 2473US10379857B2Dynamic sequential instruction prefetchingIBM·Filed 2018·Granted Aug 13, 2019·1 cites·20 claims
- 2573US6279105B1Pipelined two-cycle branch target address cacheIBM·Filed 1998·Granted Aug 21, 2001·62 cites·16 claims
- 2673US5553255AData processor with programmable levels of speculative instruction fetching and method of operationMOTOROLA INC·Filed 1995·Granted Sep 3, 1996·83 cites·6 claims
- 2772US10795683B2Predicting indirect branches using problem branch filtering and pattern cacheIBM·Filed 2014·Granted Oct 6, 2020·3 cites·8 claims
- 2872US9495164B2Branch prediction using multiple versions of history dataIBM·Filed 2016·Granted Nov 15, 2016·1 cites·1 claims
- 2972US7865705B2Branch target address cache including address type tag bitIBM·Filed 2008·Granted Jan 4, 2011·5 cites·12 claims
- 3070US9189365B2Hardware-assisted program trace collection with selectable call-signature captureIBM·Filed 2013·Granted Nov 17, 2015·2 cites·12 claims
- 3169US10175987B2Instruction prefetching in a computer processor using a prefetch prediction vectorIBM·Filed 2016·Granted Jan 8, 2019·1 cites·18 claims
- 3269US9483271B2Compressed indirect prediction cachesIBM·Filed 2013·Granted Nov 1, 2016·2 cites·20 claims
- 3367US8370671B2Saving power by powering down an instruction fetch array based on capacity history of instruction bufferIBM·Filed 2009·Granted Feb 5, 2013·3 cites·24 claims
- 3466US5872950AMethod and apparatus for managing register renaming including a wraparound array and an indication of rename entry agesIBM·Filed 1997·Granted Feb 16, 1999·49 cites·4 claims
- 3565US8635408B2Controlling power of a cache based on predicting the instruction cache way for high power applicationsLEVENSTEIN SHELDON B·Filed 2011·Granted Jan 21, 2014·2 cites·18 claims
- 3665US7426631B2Methods and systems for storing branch information in an address table of a processorIBM·Filed 2005·Granted Sep 16, 2008·2 cites·8 claims
- 3765US7000233B2Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective threadIBM·Filed 2003·Granted Feb 14, 2006·10 cites·25 claims
- 3865US5758143AMethod for updating a branch history table in a processor which resolves multiple branches in a single cycleIBM·Filed 1996·Granted May 26, 1998·43 cites·16 claims
- 3964US7039768B2Cache predictor for simultaneous multi-threaded processor system supporting multiple transactionsIBM·Filed 2003·Granted May 2, 2006·10 cites·36 claims
- 4064US6651162B1Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cacheIBM·Filed 1999·Granted Nov 18, 2003·41 cites·21 claims
- 4163US7962722B2Branch target address cache with hashed indicesIBM·Filed 2008·Granted Jun 14, 2011·2 cites·15 claims
- 4260US10664279B2Instruction prefetching in a computer processor using a prefetch prediction vectorIBM·Filed 2019·Granted May 26, 2020·0 cites·18 claims
- 4360US7412620B2Method for testing ability to recover from cache directory errorsIBM·Filed 2005·Granted Aug 12, 2008·1 cites·8 claims
- 4459US10552159B2Power management of branch predictors in a computer processorIBM·Filed 2018·Granted Feb 4, 2020·0 cites·17 claims
- 4558US9904551B2Branch prediction using multiple versions of history dataIBM·Filed 2016·Granted Feb 27, 2018·0 cites·1 claims
- 4658US9898295B2Branch prediction using multiple versions of history dataIBM·Filed 2016·Granted Feb 20, 2018·0 cites·1 claims
- 4756US6662360B1Method and system for software control of hardware branch prediction mechanism in a data processorIBM·Filed 1999·Granted Dec 9, 2003·31 cites·8 claims
- 4855US9081895B2Identifying and tagging breakpoint instructions for facilitation of software debugIBM·Filed 2013·Granted Jul 14, 2015·0 cites·8 claims
- 4954US7984280B2Storing branch information in an address table of a processorIBM·Filed 2008·Granted Jul 19, 2011·0 cites·6 claims
- 5054US5894487AError detection of directory arrays in dynamic circuitsIBM·Filed 1997·Granted Apr 13, 1999·14 cites·28 claims
Showing the top 50 of 81 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when David S. Levitan files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →