Inventor · disambiguated record
Sunil Shenoy
Also filed as: SHENOY SUNIL · SHENOY SUNIL R
16 granted patents·1,023 citations·filing 1987–1998
96Inventor score
Files withINTEL CORP16
Top patents by PatentIndex Score
16 records- 0195US5604877AMethod and apparatus for resolving return from subroutine instructions in a computer processorINTEL CORP·Filed 1994·Granted Feb 18, 1997·209 cites·28 claims
- 0291US5574871AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1994·Granted Nov 12, 1996·122 cites·17 claims
- 0390US5493667AApparatus and method for an instruction cache locking schemeINTEL CORP·Filed 1993·Granted Feb 20, 1996·162 cites·67 claims
- 0484US5812839ADual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unitINTEL CORP·Filed 1997·Granted Sep 22, 1998·118 cites·32 claims
- 0579US5768576AMethod and apparatus for predicting and handling resolving return from subroutine instructions in a computer processorINTEL CORP·Filed 1996·Granted Jun 16, 1998·75 cites·19 claims
- 0676US4785428AProgrammable memory array control signalsINTEL CORP·Filed 1987·Granted Nov 15, 1988·35 cites·10 claims
- 0768US5903751AMethod and apparatus for implementing a branch target buffer in CISC processorINTEL CORP·Filed 1997·Granted May 11, 1999·38 cites·3 claims
- 0867US5870599AComputer system employing streaming buffer for instruction preetchingINTEL CORP·Filed 1997·Granted Feb 9, 1999·51 cites·36 claims
- 0965US5455924AApparatus and method for partial execution blocking of instructions following a data cache missINTEL CORP·Filed 1993·Granted Oct 3, 1995·47 cites·63 claims
- 1061US5574923AMethod and apparatus for performing bi-endian byte and short accesses in a single-endian microprocessorINTEL CORP·Filed 1993·Granted Nov 12, 1996·37 cites·24 claims
- 1160US5944817AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1998·Granted Aug 31, 1999·27 cites·4 claims
- 1259US5590368AMethod and apparatus for dynamically expanding the pipeline of a microprocessorINTEL CORP·Filed 1995·Granted Dec 31, 1996·43 cites·9 claims
- 1355US5706492AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1996·Granted Jan 6, 1998·22 cites·19 claims
- 1444US5313605AHigh bandwith output hierarchical memory store including a cache, fetch buffer and ROMINTEL CORP·Filed 1990·Granted May 17, 1994·17 cites·2 claims
- 1540US5749092AMethod and apparatus for using a direct memory access unit and a data cache unit in a microprocessorINTEL CORP·Filed 1997·Granted May 5, 1998·15 cites·17 claims
- 1631US4821271AMethods and circuits for checking integrated circuit chips having programmable outputsINTEL CORP·Filed 1987·Granted Apr 11, 1989·5 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →