Inventor · disambiguated record
Antonio R. Pelella
Also filed as: PELELLA ANTONIO · PELELLA ANTONIO R · PELELLA ANTONIO RAFFAELE
37 granted patents·3 pending applications·331 citations·filing 1994–2024
97Inventor score
Top patents by PatentIndex Score
40 records- 0195US7102946B2Local bit select circuit with slow read recovery schemeIBM·Filed 2005·Granted Sep 5, 2006·41 cites·20 claims
- 0293US9742408B1Dynamic decode circuit with active glitch controlIBM·Filed 2016·Granted Aug 22, 2017·8 cites·15 claims
- 0391US9966958B2Dynamic decode circuit with active glitch controlIBM·Filed 2017·Granted May 8, 2018·8 cites·12 claims
- 0489US7113433B2Local bit select with suppression of fast read before writeIBM·Filed 2005·Granted Sep 26, 2006·23 cites·2 claims
- 0589US5576644AFast edge triggered self-resetting CMOS receiver with parallel L1/L2 (master/slave) latchIBM·Filed 1995·Granted Nov 19, 1996·54 cites·7 claims
- 0681US10367507B2Dynamic decode circuit with active glitch controlIBM·Filed 2018·Granted Jul 30, 2019·3 cites·19 claims
- 0780US7336546B2Global bit select circuit with dual read and write bit line pairsIBM·Filed 2005·Granted Feb 26, 2008·11 cites·1 claims
- 0880US6868000B2Coupled body contacts for SOI differential circuitsIBM·Filed 2003·Granted Mar 15, 2005·27 cites·31 claims
- 0979US6788112B1High performance dual-stage sense amplifier circuitIBM·Filed 2003·Granted Sep 7, 2004·30 cites·25 claims
- 1076US7170774B2Global bit line restore timing scheme and circuitIBM·Filed 2005·Granted Jan 30, 2007·9 cites·20 claims
- 1175US7272030B2Global bit line restore timing scheme and circuitIBM·Filed 2006·Granted Sep 18, 2007·8 cites·12 claims
- 1273US7293209B2Split L2 latch with glitch free programmable delayIBM·Filed 2005·Granted Nov 6, 2007·7 cites·2 claims
- 1373US5465060AFast edge triggered self-resetting CMOS receiver with parallel L1/L2 (Master/Slave) latchIBM·Filed 1994·Granted Nov 7, 1995·21 cites·7 claims
- 1472US7463537B2Global bit select circuit interface with dual read and write bit line pairsIBM·Filed 2007·Granted Dec 9, 2008·7 cites·1 claims
- 1569US10374604B1Dynamic decode circuit low power applicationIBM·Filed 2018·Granted Aug 6, 2019·1 cites·20 claims
- 1661US8233331B2Single clock dynamic compare circuitCHAN YUEN H·Filed 2010·Granted Jul 31, 2012·2 cites·16 claims
- 1756US10454477B1Dynamic decode circuit low power applicationIBM·Filed 2019·Granted Oct 22, 2019·0 cites·20 claims
- 1855US5764656AMethod for a fast scan GRA cell circuitIBM·Filed 1997·Granted Jun 9, 1998·9 cites·3 claims
- 1955US5552745ASelf-resetting CMOS multiplexer with static output driverIBM·Filed 1994·Granted Sep 3, 1996·10 cites·16 claims
- 2055US2025391468A1Nor decoder for large decode structuresIBM·Filed 2024·Application pending·0 cites
- 2154US8638595B2Global bit select circuit with write around capabilityPELELLA ANTONIO R·Filed 2012·Granted Jan 28, 2014·2 cites·20 claims
- 2253US10312915B2Dynamic decode circuit with active glitch control methodIBM·Filed 2018·Granted Jun 4, 2019·0 cites·20 claims
- 2353US10312916B2Dynamic decode circuit with delayed prechargeIBM·Filed 2018·Granted Jun 4, 2019·0 cites·15 claims
- 2452US10320388B2Dynamic decode circuit with active glitch control methodIBM·Filed 2018·Granted Jun 11, 2019·0 cites·19 claims
- 2552US5748643AFast scan GRA cell circuitIBM·Filed 1996·Granted May 5, 1998·16 cites·7 claims
- 2651US10224933B2Dynamic decode circuit with active glitch controlIBM·Filed 2017·Granted Mar 5, 2019·0 cites·16 claims
- 2750US7170799B2SRAM and dual single ended bit sense for an SRAMIBM·Filed 2005·Granted Jan 30, 2007·2 cites·26 claims
- 2849US8184475B2Robust local bit select circuitry to overcome timing mismatchJOSHI RAJIV V·Filed 2010·Granted May 22, 2012·1 cites·20 claims
- 2948US7592851B2High performance pseudo dynamic pulse controllable multiplexerIBM·Filed 2008·Granted Sep 22, 2009·2 cites·14 claims
- 3048US5568076AMethod of converting short duration input pulses to longer duration output pulsesIBM·Filed 1995·Granted Oct 22, 1996·8 cites·5 claims
- 3145US7054184B2Cache late select circuitIBM·Filed 2004·Granted May 30, 2006·5 cites·4 claims
- 3241US5740412ASet-select multiplexer with an array built-in self-test featureIBM·Filed 1996·Granted Apr 14, 1998·8 cites·13 claims
- 3340US6646544B1Self timed pre-charged address compare logic circuitIBM·Filed 2002·Granted Nov 11, 2003·0 cites·8 claims
- 3438US11682452B2Local bit select with improved fast read before write suppressionIBM·Filed 2021·Granted Jun 20, 2023·0 cites·19 claims
- 3537US5982203ATwo stage SRCMOS sense amplifierIBM·Filed 1998·Granted Nov 9, 1999·5 cites·8 claims
- 3634US5528178ASense and hold amplifierIBM·Filed 1995·Granted Jun 18, 1996·3 cites·8 claims
- 3733US7084673B2Output driver with pulse to static converterIBM·Filed 2004·Granted Aug 1, 2006·0 cites·2 claims
- 3832US2011317478A1Method and Circuit Arrangement for Performing a Write Through Operation, and SRAM Array With Write Through CapabilityCHAN YUEN H·Filed 2011·Application pending·0 cites
- 3932US2011296259A1Testing memory arrays and logic with abist circuitryBALAKRISHNAN BARGAV·Filed 2010·Application pending·0 cites
- 4030US5614849AMethod of resetting a CMOS amplifierIBM·Filed 1995·Granted Mar 25, 1997·0 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →