Inventor · disambiguated record
Robert J. Stoll
Also filed as: STOLL ROBERT · STOLL ROBERT J · STOLL ROBERT JAMES
16 granted patents·1 pending application·183 citations·filing 2006–2015
92Inventor score
Top patents by PatentIndex Score
17 records- 0194US8266383B1Cache miss processing using a defer/replay mechanismMINKIN ALEXANDER L·Filed 2009·Granted Sep 11, 2012·51 cites·20 claims
- 0294US8233004B1Color-compression using automatic reduction of multi-sampled pixelsMOLNAR STEVEN E·Filed 2006·Granted Jul 31, 2012·42 cites·16 claims
- 0393US7692659B1Color-compression using automatic reduction of multi-sampled pixelsNVIDIA CORP·Filed 2006·Granted Apr 6, 2010·36 cites·20 claims
- 0490US8732713B2Thread group scheduler for computing on a parallel thread processorCOON BRETT W·Filed 2011·Granted May 20, 2014·15 cites·20 claims
- 0587US9471307B2System and processor that include an implementation of decoupled pipelinesNVIDIA CORP·Filed 2014·Granted Oct 18, 2016·10 cites·16 claims
- 0683US7791611B1Asynchronous reorder bufferNVIDIA CORP·Filed 2006·Granted Sep 7, 2010·16 cites·7 claims
- 0774US8949841B2Approach for a configurable phase-based priority schedulerNVIDIA CORP·Filed 2012·Granted Feb 3, 2015·3 cites·21 claims
- 0871US9189242B2Credit-based streaming multiprocessor warp schedulingLINDHOLM JOHN ERIK·Filed 2010·Granted Nov 17, 2015·3 cites·23 claims
- 0966US9830158B2Speculative execution and rollbackCHOQUETTE JACK HILAIRE·Filed 2011·Granted Nov 28, 2017·2 cites·28 claims
- 1060US8125489B1Processing pipeline with latency bypassHOLMQVIST PETER B·Filed 2006·Granted Feb 28, 2012·4 cites·16 claims
- 1154US7725688B1System and method for storing states used to configure a processing pipeline in a graphics processing unitNVIDIA CORP·Filed 2006·Granted May 25, 2010·1 cites·17 claims
- 1250US10346212B2Approach for a configurable phase-based priority schedulerNVIDIA CORP·Filed 2015·Granted Jul 9, 2019·0 cites·24 claims
- 1349US10489200B2Hierarchical staging areas for scheduling threads for executionNVIDIA CORP·Filed 2013·Granted Nov 26, 2019·0 cites·24 claims
- 1448US9798544B2Reordering buffer for memory access localityNVIDIA CORP·Filed 2012·Granted Oct 24, 2017·0 cites·23 claims
- 1545US9798548B2Methods and apparatus for scheduling instructions using pre-decode dataCHOQUETTE JACK HILAIRE·Filed 2011·Granted Oct 24, 2017·0 cites·20 claims
- 1640US2013166882A1Methods and apparatus for scheduling instructions without instruction decodeCHOQUETTE JACK HILAIRE·Filed 2011·Application pending·0 cites
- 1738US9606808B2Method and system for resolving thread divergencesCHOQUETTE JACK·Filed 2012·Granted Mar 28, 2017·0 cites·22 claims
Join the waitlist — get patent alerts
Get an alert when Robert J. Stoll files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →