Inventor · disambiguated record
Jack H. Choquette
Also filed as: CHOQUETTE JACK · CHOQUETTE JACK H · CHOQUETTE JACK HILAIRE
88 granted patents·26 pending applications·836 citations·filing 1997–2025
99Inventor score
Files withNVIDIA CORP74AZUL SYSTEMS INC9SANDCRAFT INC8CHOQUETTE JACK HILAIRE5RAZA MICROELECTRONICS INC4
Top patents by PatentIndex Score
114 records- 0198US10338919B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2017·Granted Jul 2, 2019·24 cites·20 claims
- 0297US7337339B1Multi-level power monitoring, filtering and throttling at local blocks and globallyAZUL SYSTEMS INC·Filed 2005·Granted Feb 26, 2008·126 cites·17 claims
- 0396US7437597B1Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean linesAZUL SYSTEMS INC·Filed 2005·Granted Oct 14, 2008·71 cites·16 claims
- 0495US11816482B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2022·Granted Nov 14, 2023·2 cites·20 claims
- 0595US11138009B2Robust, efficient multiprocessor-coprocessor interfaceNVIDIA CORP·Filed 2018·Granted Oct 5, 2021·13 cites·21 claims
- 0695US7376800B1Speculative multiaddress atomicityAZUL SYSTEMS INC·Filed 2005·Granted May 20, 2008·54 cites·28 claims
- 0794US11392829B1Managing data sparsity for neural networksNVIDIA CORP·Filed 2019·Granted Jul 19, 2022·35 cites·20 claims
- 0892US11080051B2Techniques for efficiently transferring data to a processorNVIDIA CORP·Filed 2019·Granted Aug 3, 2021·9 cites·26 claims
- 0992US10884734B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2019·Granted Jan 5, 2021·5 cites·20 claims
- 1091US12141082B2Method and apparatus for efficient access to multidimensional data structures and/or other large data blocksNVIDIA CORP·Filed 2022·Granted Nov 12, 2024·4 cites·25 claims
- 1191US12020035B2Programmatically controlled data multicasting across multiple compute enginesNVIDIA CORP·Filed 2022·Granted Jun 25, 2024·3 cites·21 claims
- 1290US8732713B2Thread group scheduler for computing on a parallel thread processorCOON BRETT W·Filed 2011·Granted May 20, 2014·15 cites·20 claims
- 1389US10725837B1Persistent scratchpad memory for data exchange between programsNVIDIA CORP·Filed 2019·Granted Jul 28, 2020·9 cites·18 claims
- 1489US7552302B1Ordering operationAZUL SYSTEMS INC·Filed 2005·Granted Jun 23, 2009·14 cites·31 claims
- 1587US10977037B2Techniques for comprehensively synchronizing execution threadsNVIDIA CORP·Filed 2019·Granted Apr 13, 2021·5 cites·20 claims
- 1687US9471307B2System and processor that include an implementation of decoupled pipelinesNVIDIA CORP·Filed 2014·Granted Oct 18, 2016·10 cites·16 claims
- 1787US6480872B1Floating-point and integer multiply-add and multiply-accumulateSANDCRAFT INC·Filed 1999·Granted Nov 12, 2002·137 cites·20 claims
- 1885US8544020B1Cooperative preemptionTENE GIL·Filed 2005·Granted Sep 24, 2013·8 cites·38 claims
- 1985US7844862B1Detecting software race conditionsAZUL SYSTEMS INC·Filed 2007·Granted Nov 30, 2010·13 cites·25 claims
- 2085US2025362910A1Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2025·Application pending·0 cites
- 2184US12499052B2Method and apparatus for efficient access to multidimensional data structures and/or other large data blocksNVIDIA CORP·Filed 2022·Granted Dec 16, 2025·1 cites·16 claims
- 2283US7225300B1Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor systemAZUL SYSTEMS INC·Filed 2004·Granted May 29, 2007·36 cites·20 claims
- 2381US12321743B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2023·Granted Jun 3, 2025·0 cites·20 claims
- 2481US11803380B2High performance synchronization mechanisms for coordinating operations on a computer systemNVIDIA CORP·Filed 2019·Granted Oct 31, 2023·2 cites·22 claims
- 2580US10459861B2Unified cache for diverse memory trafficNVIDIA CORP·Filed 2017·Granted Oct 29, 2019·2 cites·21 claims
- 2680US9361114B1Instruction based interrupt masking for managing interrupts in a computer environmentTENE GIL·Filed 2005·Granted Jun 7, 2016·11 cites·16 claims
- 2779US10877757B2Binding constants at runtime for improved resource utilizationNVIDIA CORP·Filed 2018·Granted Dec 29, 2020·3 cites·20 claims
- 2879US10032245B2Techniques for maintaining atomicity and ordering for pixel shader operationsNVIDIA CORP·Filed 2015·Granted Jul 24, 2018·3 cites·22 claims
- 2979US9612836B2System, method, and computer program product for implementing software-based scoreboardingNVIDIA CORP·Filed 2014·Granted Apr 4, 2017·5 cites·19 claims
- 3079US8522000B2Trap handler architecture for a parallel processing unitSHEBANOW MICHAEL C·Filed 2009·Granted Aug 27, 2013·11 cites·20 claims
- 3178US9430242B2Throttling instruction issue rate based on updated moving average to avoid surges in DI/DTNELSON PETER MICHAEL·Filed 2012·Granted Aug 30, 2016·7 cites·20 claims
- 3277US10055806B2Techniques for maintaining atomicity and ordering for pixel shader operationsNVIDIA CORP·Filed 2015·Granted Aug 21, 2018·2 cites·22 claims
- 3377US9477482B2System, method, and computer program product for implementing multi-cycle register file bypassNVIDIA CORP·Filed 2013·Granted Oct 25, 2016·4 cites·20 claims
- 3477US9110810B2Multi-level instruction cache prefetchingWANG NICHOLAS·Filed 2011·Granted Aug 18, 2015·6 cites·20 claims
- 3577US2024169472A1Storage of transformed tensor in a cacheNVIDIA CORP·Filed 2022·Application pending·0 cites
- 3677US2024169469A1Application programming interface to transform information corresponding to a memory transactionNVIDIA CORP·Filed 2022·Application pending·0 cites
- 3777US2024168659A1Application programming interface to transform and store information corresponding to a memory transactionNVIDIA CORP·Filed 2022·Application pending·0 cites
- 3877US2024168765A1Storage of tensor in a cacheNVIDIA CORP·Filed 2022·Application pending·0 cites
- 3977US2024168831A1Application programming interface to translate a tensor according to a tensor mapNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4077US2024169471A1Storage of information in a graphics processing unit cacheNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4177US2024168830A1Application programming interface to indicate storage locationsNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4276US11816481B2Generalized acceleration of matrix multiply accumulate operationsNVIDIA CORP·Filed 2022·Granted Nov 14, 2023·0 cites·20 claims
- 4376US2024168829A1Application programming interface to generate a tensor mappingNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4476US2024169470A1Application programming interface to store information in a plurality of storage locationsNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4576US2024161223A1Application programming interface to translate a tensorNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4676US2024161224A1Application programming interface to generate a tensor according to a tensor mapNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4776US2025383879A1Scalarization of instructions for simt architecturesNVIDIA CORP·Filed 2025·Application pending·0 cites
- 4876US2024161222A1Application programming interface to indicate image-to-column transformationNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4975US10019776B2Techniques for maintaining atomicity and ordering for pixel shader operationsNVIDIA CORP·Filed 2015·Granted Jul 10, 2018·2 cites·22 claims
- 5075US7577801B1Array accessAZUL SYSTEMS INC·Filed 2005·Granted Aug 18, 2009·7 cites·37 claims
Showing the top 50 of 114 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →