Inventor · disambiguated record
Nadia M. Rahhal-Orabi
Also filed as: RAHHAL-ORABI NADIA · RAHHAL-ORABI NADIA M
30 granted patents·8 pending applications·231 citations·filing 2004–2025
96Inventor score
Top patents by PatentIndex Score
38 records- 0198US11887891B2Self-aligned contactsINTEL CORP·Filed 2023·Granted Jan 30, 2024·2 cites·20 claims
- 0298US8436404B2Self-aligned contactsBOHR MARK T·Filed 2009·Granted May 7, 2013·148 cites·30 claims
- 0397US9508821B2Self-aligned contactsINTEL CORP·Filed 2015·Granted Nov 29, 2016·13 cites·3 claims
- 0495US9093513B2Self-aligned contactsBOHR MARK T·Filed 2013·Granted Jul 28, 2015·12 cites·14 claims
- 0591US10930557B2Self-aligned contactsINTEL CORP·Filed 2020·Granted Feb 23, 2021·2 cites·12 claims
- 0688US9508796B2Internal spacers for nanowire transistors and method of fabrication thereofINTEL CORP·Filed 2013·Granted Nov 29, 2016·9 cites·18 claims
- 0787US12266571B2Self-aligned contactsINTEL CORP·Filed 2023·Granted Apr 1, 2025·0 cites·16 claims
- 0886US10141226B2Self-aligned contactsINTEL CORP·Filed 2017·Granted Nov 27, 2018·2 cites·27 claims
- 0982US9935205B2Internal spacers for nanowire transistors and method of fabrication thereofINTEL CORP·Filed 2016·Granted Apr 3, 2018·3 cites·8 claims
- 1082US2025239486A1Self-aligned contactsINTEL CORP·Filed 2025·Application pending·0 cites
- 1181US7968395B2Systems and methods for reducing contact to gate shortsINTEL CORP·Filed 2009·Granted Jun 28, 2011·7 cites·7 claims
- 1279US10431690B2High electron mobility transistors with localized sub-fin isolationINTEL CORP·Filed 2015·Granted Oct 1, 2019·3 cites·20 claims
- 1376US11600524B2Self-aligned contactsINTEL CORP·Filed 2021·Granted Mar 7, 2023·0 cites·12 claims
- 1476US7655986B2Systems and methods for reducing contact to gate shortsINTEL CORP·Filed 2006·Granted Feb 2, 2010·5 cites·8 claims
- 1575US10580865B2Transistor with a sub-fin dielectric region under a gateINTEL CORP·Filed 2015·Granted Mar 3, 2020·2 cites·17 claims
- 1673US10461082B2Well-based integration of heteroepitaxial N-type transistors with P-type transistorsINTEL CORP·Filed 2015·Granted Oct 29, 2019·2 cites·20 claims
- 1770US9224794B2Embedded memory device having MIM capacitor formed in excavated structureINTEL CORP·Filed 2013·Granted Dec 29, 2015·1 cites·6 claims
- 1868US7314836B2Enhanced nitride layers for metal oxide semiconductorsINTEL CORP·Filed 2004·Granted Jan 1, 2008·12 cites·17 claims
- 1967US10629483B2Self-aligned contactsINTEL CORP·Filed 2018·Granted Apr 21, 2020·0 cites·20 claims
- 2067US9929273B2Apparatus and methods of forming fin structures with asymmetric profileINTEL CORP·Filed 2014·Granted Mar 27, 2018·1 cites·20 claims
- 2166US7927959B2Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced therebyINTEL CORP·Filed 2008·Granted Apr 19, 2011·3 cites·15 claims
- 2263US8441057B2Embedded memory device having MIM capacitor formed in excavated structureKEATING STEVEN J·Filed 2011·Granted May 14, 2013·1 cites·7 claims
- 2363US7709866B2Method for forming semiconductor contactsINTEL CORP·Filed 2007·Granted May 4, 2010·3 cites·19 claims
- 2462US9892967B2Self-aligned contactsINTEL CORP·Filed 2016·Granted Feb 13, 2018·0 cites·8 claims
- 2547US11631737B2Ingaas epi structure and wet etch process for enabling III-v GAA in art trenchINTEL CORP·Filed 2014·Granted Apr 18, 2023·0 cites·16 claims
- 2646US2023232633A1Vertical wordline driver structures and methodsIntel NDTM US LLC·Filed 2023·Application pending·0 cites
- 2746US2017323955A1Apparatus and methods of forming fin structures with sidewall linerINTEL CORP·Filed 2014·Application pending·0 cites
- 2846US2017317187A1Uniform Layers Formed with Aspect Ratio Trench Based ProcessesINTEL CORP·Filed 2014·Application pending·0 cites
- 2944US11205707B2Optimizing gate profile for performance and gate fillINTEL CORP·Filed 2014·Granted Dec 21, 2021·0 cites·17 claims
- 3044US8168488B2Systems and methods for reducing contact to gate shortsRAHHAL-ORABI NADIA·Filed 2011·Granted May 1, 2012·0 cites·6 claims
- 3143US9142421B2Double patterning lithography techniquesWALLACE CHARLES H·Filed 2011·Granted Sep 22, 2015·0 cites·25 claims
- 3242US10797150B2Differential work function between gate stack metals to reduce parasitic capacitanceINTEL CORP·Filed 2015·Granted Oct 6, 2020·0 cites·16 claims
- 3342US9916988B2Sacrificial material for stripping masking layersINTEL CORP·Filed 2013·Granted Mar 13, 2018·0 cites·20 claims
- 3442US2017323963A1Thin channel region on wide subfinINTEL CORP·Filed 2014·Application pending·0 cites
- 3541US9305771B2Prevention of metal loss in wafer processingINTEL CORP·Filed 2013·Granted Apr 5, 2016·0 cites·14 claims
- 3638US2008206991A1Methods of forming transistor contacts and via openingsRAHHAL-ORABI NADIA·Filed 2007·Application pending·0 cites
- 3734US2010171156A1Method for Forming Semiconductor ContactsRAHHAL-ORABI NADIA·Filed 2010·Application pending·0 cites
- 3832US2007218685A1Method of forming trench contacts for MOS transistorsSIVAKUMAR SWAMINATHAN·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →