Inventor · disambiguated record
Claus Pribbernow
Also filed as: PRIBBERNOW CLAUS
9 granted patents·4 pending applications·73 citations·filing 2003–2012
86Inventor score
Files withLSI CORP5LSI LOGIC CORP3PULLAGOUNDAPATTI SAKTHIVEL KOMARASAMY2BLOCK STEFAN G1PRIBBERNOW CLAUS1
Top patents by PatentIndex Score
13 records- 0185US8365049B2Soft-error detection for electronic-circuit registersLSI CORP·Filed 2008·Granted Jan 29, 2013·18 cites·21 claims
- 0277US7451426B2Application specific configurable logic IPLSI CORP·Filed 2005·Granted Nov 11, 2008·10 cites·16 claims
- 0377US7032190B2Integrated circuits, and design and manufacture thereofLSI LOGIC CORP·Filed 2003·Granted Apr 18, 2006·29 cites·24 claims
- 0464US7640396B2All purpose processor implementation to support different types of cache memory architecturesLSI CORP·Filed 2005·Granted Dec 29, 2009·3 cites·13 claims
- 0561US7616517B1Config logic power saving methodLSI CORP·Filed 2008·Granted Nov 10, 2009·2 cites·14 claims
- 0661US7392344B2Data-processing system and method for supporting varying sizes of cache memoryLSI CORP·Filed 2005·Granted Jun 24, 2008·2 cites·20 claims
- 0752US7117472B2Placement of a clock signal supply network during design of integrated circuitsLSI LOGIC CORP·Filed 2004·Granted Oct 3, 2006·6 cites·20 claims
- 0849US8078926B2Test pin gating for dynamic optimizationBLOCK STEFAN G·Filed 2009·Granted Dec 13, 2011·2 cites·6 claims
- 0948US8583844B2System and method for optimizing slave transaction ID width based on sparse connection in multilayer multilevel interconnect system-on-chip architecturePULLAGOUNDAPATTI SAKTHIVEL KOMARASAMY·Filed 2011·Granted Nov 12, 2013·1 cites·16 claims
- 1042US2005116738A1Integrated circuits, and design and manufacture thereofLSI LOGIC CORP·Filed 2003·Application pending·0 cites
- 1141US2007067571A1Superior cache processor landing zone to support multiple processorsPRIBBERNOW CLAUS·Filed 2005·Application pending·0 cites
- 1234US2014068125A1Memory throughput improvement using address interleavingPULLAGOUNDAPATTI SAKTHIVEL K·Filed 2012·Application pending·0 cites
- 1327US2014006644A1Address Remapping Using Interconnect Routing Identification BitsPULLAGOUNDAPATTI SAKTHIVEL KOMARASAMY·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →