Inventor · disambiguated record
Aneesh Nainani
Also filed as: NAINANI ANEESH
6 granted patents·2 pending applications·13 citations·filing 2011–2015
74Inventor score
Top patents by PatentIndex Score
8 records- 0187US9570307B2Methods of doping substrates with ALDAPPLIED MATERIALS INC·Filed 2015·Granted Feb 14, 2017·5 cites·10 claims
- 0282US9218973B2Methods of doping substrates with ALDAPPLIED MATERIALS INC·Filed 2013·Granted Dec 22, 2015·5 cites·12 claims
- 0374US9378941B2Interface treatment of semiconductor surfaces with high density low energy plasmaAPPLIED MATERIALS INC·Filed 2013·Granted Jun 28, 2016·3 cites·11 claims
- 0453US2015136214A1Solar cells having selective contacts and three or more terminalsUNIV LELAND STANFORD JUNIOR·Filed 2014·Application pending·0 cites
- 0546US9543172B2Apparatus for providing and directing heat energy in a process chamberAPPLIED MATERIALS INC·Filed 2013·Granted Jan 10, 2017·0 cites·19 claims
- 0641US8969924B2Transistor-based apparatuses, systems and methodsUNIV LELAND STANFORD JUNIOR·Filed 2013·Granted Mar 3, 2015·0 cites·16 claims
- 0740US2014273504A1Selective deposition by light exposureAPPLIED MATERIALS INC·Filed 2013·Application pending·0 cites
- 0835US8933488B2Heterostructure field effect transistor with same channel and barrier configuration for PMOS and NMOSNAINANI ANEESH·Filed 2011·Granted Jan 13, 2015·0 cites·36 claims
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