Inventor · disambiguated record
Yuh-Jier Mii
Also filed as: MII YUH-JIER
26 granted patents·4 pending applications·499 citations·filing 1996–2025
96Inventor score
Files withTAIWAN SEMICONDUCTOR MFG13TAIWAN SEMICONDUCTOR MFG CO LTD5LIU CHUNG-SHI2CHUANG HARRY HAK-LAY1DOONG YIH-YUH1
Top patents by PatentIndex Score
30 records- 0197US11990169B2Transistorless memory cellTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted May 21, 2024·2 cites·20 claims
- 0297US8999839B2Semiconductor structure having an air-gap region and a method of manufacturing the sameTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Apr 7, 2015·187 cites·20 claims
- 0396US8294212B2Methods and apparatus for SRAM bit cell with low standby current, low supply voltage and high speedWANG PING-WEI·Filed 2010·Granted Oct 23, 2012·84 cites·18 claims
- 0494US10361152B2Semiconductor structure having an air-gap region and a method of manufacturing the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Jul 23, 2019·11 cites·20 claims
- 0591US8456009B2Semiconductor structure having an air-gap region and a method of manufacturing the sameSU SHU-HUI·Filed 2010·Granted Jun 4, 2013·19 cites·20 claims
- 0691US8304906B2Partial air gap formation for providing interconnect isolation in integrated circuitsHUANG CHENG-LIN·Filed 2010·Granted Nov 6, 2012·19 cites·20 claims
- 0789US12354634B2Transistorless memory cellTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jul 8, 2025·0 cites·20 claims
- 0889US7436696B2Read-preferred SRAM cell designTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Oct 14, 2008·12 cites·18 claims
- 0988US7772868B2Accurate capacitance measurement for ultra large scale integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Aug 10, 2010·9 cites·7 claims
- 1088US7359272B2Circuit and method for an SRAM with reduced power consumptionTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Apr 15, 2008·20 cites·20 claims
- 1185US8217469B2Contact implement structure for high density designHOU YUNG-CHIN·Filed 2010·Granted Jul 10, 2012·17 cites·20 claims
- 1285US2025292816A1Transistorless memory cellTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 1383US8975749B2Method of making a semiconductor device including barrier layers for copper interconnectTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Mar 10, 2015·5 cites·20 claims
- 1482US8115500B2Accurate capacitance measurement for ultra large scale integrated circuitsDOONG YIH-YUH·Filed 2011·Granted Feb 14, 2012·5 cites·11 claims
- 1581US8524570B2Method and apparatus for improving gate contactCHUANG HARRY HAK-LAY·Filed 2010·Granted Sep 3, 2013·5 cites·13 claims
- 1679US8653664B2Barrier layers for copper interconnectLIU NAI-WEI·Filed 2010·Granted Feb 18, 2014·6 cites·20 claims
- 1774US7826252B2Read-preferred SRAM cell designTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Nov 2, 2010·3 cites·12 claims
- 1872US8048717B2Method and system for bonding 3D semiconductor devicesTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Nov 1, 2011·4 cites·18 claims
- 1969US9496217B2Method and apparatus of forming a viaTSAI HSIN-YI·Filed 2009·Granted Nov 15, 2016·5 cites·20 claims
- 2068US7880494B2Accurate capacitance measurement for ultra large scale integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Feb 1, 2011·1 cites·6 claims
- 2165US5900644ATest site and a method of monitoring via etch depths for semiconductor devicesTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted May 4, 1999·33 cites·18 claims
- 2265US5702956ATest site and a method of monitoring via etch depths for semiconductor devicesTAIWAN SEMICONDUCTOR MANUFACTO·Filed 1996·Granted Dec 30, 1997·33 cites·20 claims
- 2364US11094361B2Transistorless memory cellTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Aug 17, 2021·0 cites·20 claims
- 2463US8680597B2Method and apparatus for improving gate contactTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Mar 25, 2014·1 cites·20 claims
- 2552US9123553B2Method and system for bonding 3D semiconductor deviceLIU CHUNG-SHI·Filed 2011·Granted Sep 1, 2015·0 cites·20 claims
- 2647US2015318367A1Controlling Gate Formation for High Density Cell LayoutTAIWAN SEMICONDUCTOR MFG·Filed 2015·Application pending·0 cites
- 2744US2008185722A1Formation process of interconnect structures with air-gaps and sidewall spacersLIU CHUNG-SHI·Filed 2007·Application pending·0 cites
- 2841US5966628AProcess design for wafer edge in vlsiTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Oct 12, 1999·10 cites·11 claims
- 2938US6114747AProcess design for wafer edge in VLSITAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Sep 5, 2000·8 cites·8 claims
- 3032US2006091566A1Bond pad structure for integrated circuit chipYANG CHIN-TIEN·Filed 2004·Application pending·0 cites
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