Inventor · disambiguated record
Lie-Szu Juang
Also filed as: JUANG LIE-SZU
6 granted patents·1 pending application·21 citations·filing 2007–2025
76Inventor score
Technology areasG06F
Top patents by PatentIndex Score
7 records- 0184US7640520B2Design flow for shrinking circuits having non-shrinkable IP layoutTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Dec 29, 2009·15 cites·17 claims
- 0283US2025348646A1Method and system for determining equivalence of design rule manual data and design rule checking dataTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0376US12450412B2Method and system for determining equivalence of design rule manual data and design rule checking dataTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Oct 21, 2025·0 cites·20 claims
- 0468US11842133B2Method and system for determining equivalence of design rule manual data and design rule checking dataTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Dec 12, 2023·0 cites·20 claims
- 0568US8504965B2Method for non-shrinkable IP integrationLIU HUNG-YI·Filed 2010·Granted Aug 6, 2013·3 cites·20 claims
- 0664US11120186B2Method and system for determining equivalence of design rule manual data and design rule checking dataTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 14, 2021·0 cites·20 claims
- 0764US8671367B2Integrated circuit design in optical shrink technology nodeWANG CHUNG-HSING·Filed 2008·Granted Mar 11, 2014·3 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →