Inventor · disambiguated record
Avigdor Willenz
Also filed as: WILLENZ AVIGDOR
18 granted patents·524 citations·filing 1990–2011
95Inventor score
Files withINTEGRATED DEVICE TECH9GALILEO TECHNOLOGIES LTD4SHEMLA DAVID2MARVELL ISRAEL MISL LTD1MARVELL SEMICONDUCTOR INTERNAT1
Top patents by PatentIndex Score
18 records- 0191US5398211AStructure and method for providing prioritized arbitration in a dual port memoryINTEGRATED DEVICE TECH·Filed 1993·Granted Mar 14, 1995·127 cites·10 claims
- 0279US5923660ASwitching ethernet controllerGALILEO TECHNOLOGIES LTD·Filed 1997·Granted Jul 13, 1999·81 cites·2 claims
- 0377US5841722AFirst-in, first-out (FIFO) bufferGALILEO TECHNOLOGIES LTD·Filed 1997·Granted Nov 24, 1998·83 cites·2 claims
- 0469USRE38821ESwitching ethernet controllerMARVELL SEMICONDUCTOR ISRAEL·Filed 2001·Granted Oct 11, 2005·9 cites·38 claims
- 0560US5999981ASwitching ethernet controller providing packet routingGALILEO TECHNOLOGIES LTD·Filed 1997·Granted Dec 7, 1999·40 cites·4 claims
- 0656US5809557AMemory array comprised of multiple FIFO devicesGALILEO TECHNOLOGIES LTD·Filed 1997·Granted Sep 15, 1998·38 cites·13 claims
- 0753USRE39514ESwitching ethernet controllerMARVELL SEMICONDUCTOR INTERNAT·Filed 2004·Granted Mar 13, 2007·3 cites·28 claims
- 0850US5586303AStructure and method for providing a cache memory of selectable sizesINTEGRATED DEVICE TECH·Filed 1995·Granted Dec 17, 1996·26 cites·2 claims
- 0950US5175859AApparatus for disabling unused cache tag input/output pins during processor reset by sensing pull-down resistors connected to disabled pinsINTEGRATED DEVICE TECH·Filed 1990·Granted Dec 29, 1992·22 cites·5 claims
- 1049US5386579AMinimum pin-count multiplexed address/data bus with byte enable and burst address counter support microprocessor transmitting byte enable signals on multiplexed address/data bus having burst address counter for supporting signal datum and burst transferINTEGRATED DEVICE TECH·Filed 1991·Granted Jan 31, 1995·25 cites·14 claims
- 1148USRE44151ESwitching ethernet controllerSHEMLA DAVID·Filed 2011·Granted Apr 16, 2013·0 cites·22 claims
- 1247USRE43058ESwitching ethernet controllerSHEMLA DAVID·Filed 2006·Granted Jan 3, 2012·0 cites·32 claims
- 1347US5553268AMemory operations priority scheme for microprocessorsINTEGRATED DEVICE TECH·Filed 1991·Granted Sep 3, 1996·22 cites·10 claims
- 1444USRE41464ESwitching ethernet controller providing packet routingMARVELL ISRAEL MISL LTD·Filed 2001·Granted Jul 27, 2010·0 cites·21 claims
- 1543US5649232AStructure and method for multiple-level read buffer supporting optimal throttled read operations by regulating transfer rateINTEGRATED DEVICE TECH·Filed 1995·Granted Jul 15, 1997·17 cites·14 claims
- 1643US5590310AMethod and structure for data integrity in a multiple level cache systemINTEGRATED DEVICE TECH·Filed 1995·Granted Dec 31, 1996·18 cites·6 claims
- 1735US5517659AMultiplexed status and diagnostic pins in a microprocessor with on-chip cachesINTEGRATED DEVICE TECH·Filed 1994·Granted May 14, 1996·8 cites·8 claims
- 1834US5894176AFlexible reset scheme supporting normal system operation, test and emulation modesINTEGRATED DEVICE TECH·Filed 1994·Granted Apr 13, 1999·5 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →