Inventor · disambiguated record
Eric Stotzer
Also filed as: STOTZER ERIC · STOTZER ERIC J
17 granted patents·9 pending applications·298 citations·filing 1996–2025
94Inventor score
Top patents by PatentIndex Score
26 records- 0195US11068641B1Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architectureMYTHIC INC·Filed 2021·Granted Jul 20, 2021·13 cites·15 claims
- 0295US10929748B1Systems and methods for implementing operational transformations for restricted computations of a mixed-signal integrated circuitMYTHIC INC·Filed 2020·Granted Feb 23, 2021·6 cites·19 claims
- 0381US5884023AMethod for testing an integrated circuit with user definable trace functionTEXAS INSTRUMENTS INC·Filed 1996·Granted Mar 16, 1999·99 cites·19 claims
- 0479US12260165B2Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architectureMYTHIC INC·Filed 2023·Granted Mar 25, 2025·0 cites·16 claims
- 0577US8213695B2Device and software for screening the skinZOURIDAKIS GEORGE·Filed 2008·Granted Jul 3, 2012·22 cites·25 claims
- 0677US6889320B1Microprocessor with an instruction immediately next to a branch instruction for adding a constant to a program counterTEXAS INSTRUMENTS INC·Filed 2000·Granted May 3, 2005·25 cites·21 claims
- 0777US6799266B1Methods and apparatus for reducing the size of code with an exposed pipeline by encoding NOP operations as instruction operandsTEXAS INSTRUMENTS INC·Filed 2000·Granted Sep 28, 2004·24 cites·17 claims
- 0877US2025190678A1Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architectureMYTHIC INC·Filed 2025·Application pending·0 cites
- 0976US7062762B2Partitioning symmetric nodes efficiently in a split register file architectureTEXAS INSTRUMENTS INC·Filed 2002·Granted Jun 13, 2006·31 cites·16 claims
- 1070US11822376B2Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architectureMYTHIC INC·Filed 2021·Granted Nov 21, 2023·0 cites·19 claims
- 1170US7581082B2Software source transfer selects instruction word sizesTEXAS INSTRUMENTS INC·Filed 2006·Granted Aug 25, 2009·5 cites·3 claims
- 1269US6691240B1System and method of implementing variabe length delay instructions, which prevents overlapping lifetime information or values in efficient wayTEXAS INSTRUMENTS INC·Filed 2000·Granted Feb 10, 2004·14 cites·15 claims
- 1368US6892380B2Method for software pipelining of irregular conditional control loopsTEXAS INSTRUMENTS INC·Filed 2000·Granted May 10, 2005·14 cites·4 claims
- 1467US6754893B2Method for collapsing the prolog and epilog of software pipelined loopsTEXAS INSTRUMENTS INC·Filed 2000·Granted Jun 22, 2004·14 cites·12 claims
- 1565US7673119B2VLIW optional fetch packet header extends instruction set spaceTEXAS INSTRUMENTS INC·Filed 2006·Granted Mar 2, 2010·3 cites·24 claims
- 1663US2021287077A1Systems and methods for implementing operational transformations for restricted computations of a mixed-signal integrated circuitMYTHIC INC·Filed 2021·Application pending·0 cites
- 1754US11625519B2Systems and methods for intelligent graph-based buffer sizing for a mixed-signal integrated circuitMYTHIC INC·Filed 2022·Granted Apr 11, 2023·0 cites·18 claims
- 1854US8549466B2Tiered register allocationSULE DINEEL DIWAKAR·Filed 2006·Granted Oct 1, 2013·2 cites·6 claims
- 1952US6178499B1Interruptable multiple execution unit processing during operations utilizing multiple assignment of registersTEXAS INSTRUMENTS INC·Filed 1998·Granted Jan 23, 2001·26 cites·16 claims
- 2050US2007016899A1Technique for the calling of a sub-routine by a function using an intermediate sub-routineSULE DINEEL D·Filed 2006·Application pending·0 cites
- 2142US2003182511A1Apparatus and method for resolving an instruction conflict in a software pipeline nested loop procedure in a digital signal processorFiled 2002·Application pending·0 cites
- 2242US2003120899A1Apparatus and method for processing an interrupt in a software pipeline loop procedure in a digital signal processorFiled 2002·Application pending·0 cites
- 2342US2003120905A1Apparatus and method for executing a nested loop program with a software pipeline loop procedure in a digital signal processorFiled 2002·Application pending·0 cites
- 2442US2003154469A1Apparatus and method for improved execution of a software pipeline loop procedure in a digital signal processorFiled 2002·Application pending·0 cites
- 2542US2003120900A1Apparatus and method for a software pipeline loop procedure in a digital signal processorFiled 2002·Application pending·0 cites
- 2641US2003120882A1Apparatus and method for exiting from a software pipeline loop procedure in a digital signal processorFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →