Inventor · disambiguated record
Garrett M. Drapala
Also filed as: DRAPALA GARRETT · DRAPALA GARRETT M · DRAPALA GARRETT MICHAEL
40 granted patents·2 pending applications·97 citations·filing 2007–2020
97Inventor score
Top patents by PatentIndex Score
42 records- 0192US9720833B2Nested cache coherency protocol in a tiered multi-node computer systemIBM·Filed 2015·Granted Aug 1, 2017·8 cites·9 claims
- 0289US9892043B2Nested cache coherency protocol in a tiered multi-node computer systemIBM·Filed 2017·Granted Feb 13, 2018·5 cites·17 claims
- 0386US8423736B2Maintaining cache coherence in a multi-node, symmetric multiprocessing computerBLAKE MICHAEL A·Filed 2010·Granted Apr 16, 2013·10 cites·18 claims
- 0483US9244851B2Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable indexIBM·Filed 2013·Granted Jan 26, 2016·6 cites·6 claims
- 0582US8918587B2Multilevel cache hierarchy for finding a cache line on a remote nodeBRONSON TIMOTHY C·Filed 2012·Granted Dec 23, 2014·6 cites·13 claims
- 0680US10572385B2Granting exclusive cache access using locality cache coherency stateIBM·Filed 2017·Granted Feb 25, 2020·2 cites·20 claims
- 0780US9858190B2Maintaining order with parallel access data streamsIBM·Filed 2015·Granted Jan 2, 2018·3 cites·12 claims
- 0880US9594689B2Designated cache data backup during system operationIBM·Filed 2015·Granted Mar 14, 2017·3 cites·17 claims
- 0979US9734110B2Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessingIBM·Filed 2015·Granted Aug 15, 2017·3 cites·15 claims
- 1078US11550723B2Method, apparatus, and system for memory bandwidth aware data prefetchingQUALCOMM INC·Filed 2018·Granted Jan 10, 2023·2 cites·26 claims
- 1177US10042554B2Increased bandwidth of ordered stores in a non-uniform memory subsystemIBM·Filed 2015·Granted Aug 7, 2018·2 cites·7 claims
- 1275US9348524B1Memory controlled operations under dynamic relocation of storageIBM·Filed 2014·Granted May 24, 2016·3 cites·20 claims
- 1375US8364904B2Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computerIBM·Filed 2010·Granted Jan 29, 2013·4 cites·24 claims
- 1474US8762651B2Maintaining cache coherence in a multi-node, symmetric multiprocessing computerBLAKE MICHAEL A·Filed 2010·Granted Jun 24, 2014·4 cites·17 claims
- 1574US8566532B2Management of multipurpose command queues in a multilevel cache hierarchyDUNN BERGER DEANNA POSTLES·Filed 2010·Granted Oct 22, 2013·4 cites·18 claims
- 1674US8458405B2Cache bank modeling with variable access and busy timesBRONSON TIMOTHY C·Filed 2010·Granted Jun 4, 2013·4 cites·20 claims
- 1772US9852071B2Granting exclusive cache access using locality cache coherency stateIBM·Filed 2014·Granted Dec 26, 2017·2 cites·20 claims
- 1871US10528253B2Increased bandwidth of ordered stores in a non-uniform memory subsystemIBM·Filed 2014·Granted Jan 7, 2020·2 cites·13 claims
- 1971US9292445B2Non-data inclusive coherent (NIC) directory for cacheIBM·Filed 2014·Granted Mar 22, 2016·2 cites·11 claims
- 2070US9323676B2Non-data inclusive coherent (NIC) directory for cacheIBM·Filed 2013·Granted Apr 26, 2016·2 cites·8 claims
- 2168US9798663B2Granting exclusive cache access using locality cache coherency stateIBM·Filed 2015·Granted Oct 24, 2017·1 cites·10 claims
- 2268US9003125B2Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable indexAMBROLADZE EKATERINA M·Filed 2012·Granted Apr 7, 2015·2 cites·11 claims
- 2368US8560776B2Method for expediting return of line exclusivity to a given processor in a symmetric multiprocessing data processing systemDRAPALA GARRETT M·Filed 2008·Granted Oct 15, 2013·4 cites·20 claims
- 2467US7574548B2Dynamic data transfer control method and apparatus for shared SMP computer systemsIBM·Filed 2007·Granted Aug 11, 2009·4 cites·20 claims
- 2565US9495107B2Dynamic relocation of storageIBM·Filed 2014·Granted Nov 15, 2016·1 cites·20 claims
- 2665US7779189B2Method, system, and computer program product for pipeline arbitrationIBM·Filed 2008·Granted Aug 17, 2010·3 cites·18 claims
- 2764US9459998B2Operations interlock under dynamic relocation of storageIBM·Filed 2015·Granted Oct 4, 2016·1 cites·20 claims
- 2860US9727464B2Nested cache coherency protocol in a tiered multi-node computer systemDRAPALA GARRETT MICHAEL·Filed 2014·Granted Aug 8, 2017·1 cites·16 claims
- 2960US8478920B2Controlling data stream interruptions on a shared interfaceDRAPALA GARRETT M·Filed 2010·Granted Jul 2, 2013·1 cites·16 claims
- 3059US9558119B2Main memory operations in a symmetric multiprocessing computerDRAPALA GARRETT M·Filed 2010·Granted Jan 31, 2017·1 cites·15 claims
- 3157US9299456B2Matrix and compression-based error detectionIBM·Filed 2014·Granted Mar 29, 2016·0 cites·13 claims
- 3255US11226910B2Ticket based request flow controlQUALCOMM INC·Filed 2020·Granted Jan 18, 2022·0 cites·44 claims
- 3353US8972664B2Multilevel cache hierarchy for finding a cache line on a remote nodeIBM·Filed 2013·Granted Mar 3, 2015·0 cites·7 claims
- 3450US11016899B2Selectively honoring speculative memory prefetch requests based on bandwidth state of a memory access path component(s) in a processor-based systemQUALCOMM INC·Filed 2019·Granted May 25, 2021·0 cites·38 claims
- 3547US7818504B2Storage system that prioritizes storage requestsIBM·Filed 2007·Granted Oct 19, 2010·0 cites·22 claims
- 3646US7702972B2Method and apparatus for SRAM macro sparing in computer chipsIBM·Filed 2007·Granted Apr 20, 2010·1 cites·19 claims
- 3745US9268660B2Matrix and compression-based error detectionIBM·Filed 2014·Granted Feb 23, 2016·0 cites·7 claims
- 3843US9678873B2Early shared resource release in symmetric multiprocessing computer systemsIBM·Filed 2015·Granted Jun 13, 2017·0 cites·15 claims
- 3943US8688880B2Centralized serialization of requests in a multiprocessor systemDRAPALA GARRETT M·Filed 2010·Granted Apr 1, 2014·0 cites·20 claims
- 4043US8375155B2Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computerIBM·Filed 2010·Granted Feb 12, 2013·0 cites·18 claims
- 4143US2019087333A1Converting a stale cache memory unique request to a read unique snoop response in a multiple (multi-) central processing unit (cpu) processor to reduce latency associated with reissuing the stale unique requestQUALCOMM INC·Filed 2018·Application pending·0 cites
- 4242US2019013062A1Selective refresh mechanism for dramQUALCOMM INC·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →