Inventor · disambiguated record
Joel R. Phillips
Also filed as: PHILLIPS JOEL · PHILLIPS JOEL R · PHILLIPS JOEL REUBEN
31 granted patents·499 citations·filing 2000–2019
97Inventor score
Top patents by PatentIndex Score
31 records- 0196US7882471B1Timing and signal integrity analysis of integrated circuits with semiconductor process variationsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 1, 2011·56 cites·23 claims
- 0294US8245165B1Methods and apparatus for waveform based variational static timing analysisTIWARY SAURABH K·Filed 2008·Granted Aug 14, 2012·36 cites·20 claims
- 0392US8601420B1Equivalent waveform model for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2010·Granted Dec 3, 2013·27 cites·30 claims
- 0492US6349272B1Method and system for modeling time-varying systems and non-linear systemsCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Feb 19, 2002·122 cites·23 claims
- 0590US8516420B1Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source modelKARIAT VINOD·Filed 2007·Granted Aug 20, 2013·19 cites·33 claims
- 0689US11348252B1Method and apparatus for supporting augmented and/or virtual reality playback using tracked objectsNEVERMIND CAPITAL LLC·Filed 2019·Granted May 31, 2022·13 cites·10 claims
- 0789US8341572B1Methods and apparatus for waveform based variational static timing analysisTIWARY SAURABH K·Filed 2008·Granted Dec 25, 2012·17 cites·19 claims
- 0888US8966421B1Static timing analysis methods for integrated circuit designs using a multi-CCC current source modelCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Feb 24, 2015·8 cites·8 claims
- 0987US8631369B1Methods, systems, and apparatus for timing and signal integrity analysis of integrated circuits with semiconductor process variationsKARIAT VINOD·Filed 2010·Granted Jan 14, 2014·10 cites·7 claims
- 1087US8180621B2Parametric perturbations of performance metrics for integrated circuitsPHILLIPS JOEL REUBEN·Filed 2008·Granted May 15, 2012·23 cites·23 claims
- 1187US7533359B2Method and system for chip design using physically appropriate component models and extractionCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted May 12, 2009·17 cites·29 claims
- 1286US8782583B1Waveform based variational static timing analysisTIWARY SAURABH K·Filed 2012·Granted Jul 15, 2014·7 cites·9 claims
- 1384US10860767B1Systems and methods for transient simulation of circuits with mutual inductorsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Dec 8, 2020·7 cites·20 claims
- 1482US8375343B1Methods and apparatus for waveform based variational static timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Feb 12, 2013·8 cites·20 claims
- 1581US8726211B2Generating an equivalent waveform model in static timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted May 13, 2014·8 cites·29 claims
- 1675US8533644B1Multi-CCC current source models and static timing analysis methods for integrated circuit designsKARIAT VINOD·Filed 2010·Granted Sep 10, 2013·3 cites·10 claims
- 1775US8245167B1Branch and bound techniques for computation of critical timing conditionsE SILVA LUIS GUERRA·Filed 2009·Granted Aug 14, 2012·11 cites·23 claims
- 1873US7428477B1Simulation of electrical circuitsCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Sep 23, 2008·20 cites·64 claims
- 1972US8341567B1Boolean satisfiability based verification of analog circuitsTIWARY SAURABH K·Filed 2008·Granted Dec 25, 2012·7 cites·45 claims
- 2072US8325188B1Method and system for implementing a waveform viewerPHILLIPS JOEL R·Filed 2006·Granted Dec 4, 2012·9 cites·42 claims
- 2169US7493240B1Method and apparatus for simulating quasi-periodic circuit operating conditions using a mixed frequency/time algorithmCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Feb 17, 2009·13 cites·38 claims
- 2269US7035782B2Method and device for multi-interval collocation for efficient high accuracy circuit simulationCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Apr 25, 2006·17 cites·40 claims
- 2367US8799840B1Branch and bound techniques for computation of critical timing conditionsE SILVA LUIS GUERRA·Filed 2009·Granted Aug 5, 2014·6 cites·46 claims
- 2467US7487078B1Method and system for modeling distributed time invariant systemsCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Feb 3, 2009·15 cites·38 claims
- 2566US7590518B2Circuit analysis utilizing rank revealing factorizationCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Sep 15, 2009·11 cites·36 claims
- 2661US8195440B2Method and apparatus for simulating quasi-periodic circuit operating conditions using a mixed frequency/time algorithmFENG DAN·Filed 2009·Granted Jun 5, 2012·2 cites·29 claims
- 2761US7853910B1Parasitic effects analysis of circuit structuresCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Dec 14, 2010·4 cites·20 claims
- 2856US10423744B1Reduced resource harmonic balance circuit simulationsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Sep 24, 2019·1 cites·20 claims
- 2953US7996193B2Method for reducing model order exploiting sparsity in electronic design automation and analysisCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Aug 9, 2011·2 cites·20 claims
- 3040US12141233B1Method, system, and computer program product for characterizing an electronic circuit using model order reduction-based envelope fourier techniquesCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Nov 12, 2024·0 cites·20 claims
- 3139US10068044B1System and method for efficient device testing and validation of fast transientsCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 4, 2018·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →