Inventor · disambiguated record
Mark H. Nodine
Also filed as: NODINE MARK H
8 granted patents·59 citations·filing 1997–2012
83Inventor score
Technology areasG06F
Top patents by PatentIndex Score
8 records- 0166US8310268B2Generating test benches for pre-silicon validation of retimed complex IC designs against a reference designNODINE MARK H·Filed 2011·Granted Nov 13, 2012·2 cites·20 claims
- 0260US8429580B2Method for preparing for and formally verifying a modified integrated circuit designYEUNG RAYMOND C·Filed 2011·Granted Apr 23, 2013·2 cites·14 claims
- 0356US8443319B2Method for preparing re-architected designs for sequential equivalence checkingNODINE MARK H·Filed 2009·Granted May 14, 2013·2 cites·20 claims
- 0451US9053265B2Generating test benches for pre-silicon validation of retimed complex IC designs against a reference designAPPLE INC·Filed 2012·Granted Jun 9, 2015·0 cites·20 claims
- 0550US7956636B2Generating test benches for pre-silicon validation of retimed complex IC designs against a reference designAPPLE INC·Filed 2008·Granted Jun 7, 2011·0 cites·18 claims
- 0648US6106567ACircuit design verification tool and method therefor using maxwell's equationsMOTOROLA INC·Filed 1998·Granted Aug 22, 2000·23 cites·23 claims
- 0748US5966306AMethod for verifying protocol conformance of an electrical interfaceMOTOROLA INC·Filed 1997·Granted Oct 12, 1999·29 cites·23 claims
- 0844US8448107B2Method for piecewise hierarchical sequential verificationSHEELEY NATHAN FRANCIS·Filed 2009·Granted May 21, 2013·1 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →