Inventor · disambiguated record
Martin D. Giles
Also filed as: GILES MARTIN · GILES MARTIN D
37 granted patents·8 pending applications·459 citations·filing 2001–2024
97Inventor score
Top patents by PatentIndex Score
45 records- 0198US9129829B2Silicon and silicon germanium nanowire structuresKUHN KELIN J·Filed 2014·Granted Sep 8, 2015·62 cites·13 claims
- 0298US8753942B2Silicon and silicon germanium nanowire structuresKUHN KELIN J·Filed 2010·Granted Jun 17, 2014·144 cites·30 claims
- 0397US7838373B2Replacement spacers for MOSFET fringe capacitance reduction and processes of making sameINTEL CORP·Filed 2008·Granted Nov 23, 2010·52 cites·21 claims
- 0493US9595581B2Silicon and silicon germanium nanowire structuresINTEL CORP·Filed 2015·Granted Mar 14, 2017·7 cites·19 claims
- 0593US9564522B2Nanowire structures having non-discrete source and drain regionsCEA STEPHEN M·Filed 2015·Granted Feb 7, 2017·6 cites·9 claims
- 0693US9087863B2Nanowire structures having non-discrete source and drain regionsCEA STEPHEN M·Filed 2011·Granted Jul 21, 2015·10 cites·17 claims
- 0793US8558279B2Non-planar device having uniaxially strained semiconductor body and method of making sameCEA STEPHEN M·Filed 2010·Granted Oct 15, 2013·15 cites·20 claims
- 0892US6982433B2Gate-induced strain for MOS performance improvementINTEL CORP·Filed 2003·Granted Jan 3, 2006·69 cites·25 claims
- 0991US9607987B2Methods for forming fins for metal oxide semiconductor device structuresGILES MARTIN D·Filed 2011·Granted Mar 28, 2017·10 cites·17 claims
- 1091US8269283B2Methods and apparatus to reduce layout based strain variations in non-planar transistor structuresCEA STEPHEN M·Filed 2009·Granted Sep 18, 2012·18 cites·8 claims
- 1189US2025185316A1Silicon and silicon germanium nanowire structuresSONY GROUP CORP·Filed 2024·Application pending·0 cites
- 1288US9583487B2Semiconductor device having metallic source and drain regionsGILES MARTIN D·Filed 2011·Granted Feb 28, 2017·10 cites·23 claims
- 1388US8487348B2Methods and apparatus to reduce layout based strain variations in non-planar transistor structuresCEA STEPHEN M·Filed 2012·Granted Jul 16, 2013·8 cites·12 claims
- 1488US7470972B2Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stressINTEL CORP·Filed 2005·Granted Dec 30, 2008·15 cites·7 claims
- 1586US2025113607A1Fins for metal oxide semiconductor device structuresINTEL CORP·Filed 2024·Application pending·0 cites
- 1683US12125916B2Nanowire structures having non-discrete source and drain regionsGOOGLE LLC·Filed 2022·Granted Oct 22, 2024·0 cites·7 claims
- 1783US10985184B2Fins for metal oxide semiconductor device structuresINTEL CORP·Filed 2017·Granted Apr 20, 2021·2 cites·4 claims
- 1879US9224754B2Stress in trigate devices using complimentary gate fill materialsRAKSHIT TITASH·Filed 2014·Granted Dec 29, 2015·3 cites·11 claims
- 1976US12205955B2Fins for metal oxide semiconductor device structuresINTEL CORP·Filed 2021·Granted Jan 21, 2025·0 cites·17 claims
- 2076US12142634B2Silicon and silicon germanium nanowire structuresSONY GROUP CORP·Filed 2021·Granted Nov 12, 2024·0 cites·25 claims
- 2176US8362566B2Stress in trigate devices using complimentary gate fill materialsINTEL CORP·Filed 2008·Granted Jan 29, 2013·4 cites·5 claims
- 2275US7452764B2Gate-induced strain for MOS performance improvementINTEL CORP·Filed 2005·Granted Nov 18, 2008·5 cites·6 claims
- 2373US10991799B2Silicon and silicon germanium nanowire structuresSONY CORP·Filed 2020·Granted Apr 27, 2021·0 cites·19 claims
- 2472US11552197B2Nanowire structures having non-discrete source and drain regionsGOOGLE LLC·Filed 2020·Granted Jan 10, 2023·0 cites·6 claims
- 2564US10636871B2Silicon and silicon germanium nanowire structuresINTEL CORP·Filed 2017·Granted Apr 28, 2020·0 cites·19 claims
- 2660US10580899B2Nanowire structures having non-discrete source and drain regionsINTEL CORP·Filed 2017·Granted Mar 3, 2020·0 cites·17 claims
- 2758US9806193B2Stress in trigate devices using complimentary gate fill materialsINTEL CORP·Filed 2016·Granted Oct 31, 2017·0 cites·20 claims
- 2858US9450092B2Stress in trigate devices using complimentary gate fill materialsINTEL CORP·Filed 2015·Granted Sep 20, 2016·0 cites·20 claims
- 2957US7473614B2Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layerINTEL CORP·Filed 2004·Granted Jan 6, 2009·6 cites·7 claims
- 3054US8741733B2Stress in trigate devices using complimentary gate fill materialsRAKSHIT TITASH·Filed 2013·Granted Jun 3, 2014·0 cites·5 claims
- 3153US9680013B2Non-planar device having uniaxially strained semiconductor body and method of making sameINTEL CORP·Filed 2013·Granted Jun 13, 2017·0 cites·17 claims
- 3251US10847653B2Semiconductor device having metallic source and drain regionsINTEL CORP·Filed 2017·Granted Nov 24, 2020·0 cites·9 claims
- 3351US7679145B2Transistor performance enhancement using engineered strainsINTEL CORP·Filed 2004·Granted Mar 16, 2010·5 cites·21 claims
- 3451US2009096025A1Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layerTOLCHINSKY PETER G·Filed 2008·Application pending·0 cites
- 3547US7719057B2Multiple oxide thickness for a semiconductor deviceINTEL CORP·Filed 2007·Granted May 18, 2010·0 cites·20 claims
- 3647US2009075445A1Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stressKAVALIEROS JACK·Filed 2008·Application pending·0 cites
- 3746US7091560B2Method and structure to decrease area capacitance within a buried insulator deviceINTEL CORP·Filed 2004·Granted Aug 15, 2006·2 cites·16 claims
- 3846US6867104B2Method to form a structure to decrease area capacitance within a buried insulator deviceINTEL CORP·Filed 2002·Granted Mar 15, 2005·2 cites·15 claims
- 3945US2009152589A1Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate TransistorsRAKSHIT TITASH·Filed 2007·Application pending·0 cites
- 4042US6617228B2Semiconductor material and method for enhancing solubility of a dopant thereinUNIV CALIFORNIA·Filed 2002·Granted Sep 9, 2003·2 cites·9 claims
- 4142US6498078B2Method for enhancing the solubility of boron and indium in siliconUNIV CALIFORNIA·Filed 2001·Granted Dec 24, 2002·2 cites·13 claims
- 4242US2009315120A1Raised facet- and non-facet 3d source/drain contacts in mosfetsSHIFREN LUCIAN·Filed 2008·Application pending·0 cites
- 4340US2007063279A1Insulation layer for silicon-on-insulator waferTOLCHINSKY PETER G·Filed 2005·Application pending·0 cites
- 4435US6872455B2Semiconductor material and method for enhancing solubility of a dopant thereinUNIV CALIFORNIA·Filed 2003·Granted Mar 29, 2005·0 cites·3 claims
- 4532US2006226453A1Methods of forming stress enhanced PMOS structuresWANG EVERETT X·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →